System and method of monitoring, predicting and optimizing production yields in a liquid crystal display (LCD) manufacturing process

ABSTRACT

A system and method of monitoring LCD production yields, predicting the effects of different testing methodologies on LCD production yields, and optimizing production yields is provided that compares the effect of different testing methodologies on the yields at various stages in the LCD testing and assembly process. The present invention can also be used to predict the effect of different testing methodologies on user-defined parameters, such as profit.

This is a continuation of U.S. patent application Ser. No. 10/355,059 filed Jan. 31, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to LCD manufacturing and, more particularly, to a system and method of monitoring LCD production yields, predicting the effects of different testing methodologies on LCD production yields, and optimizing production yields.

2. Background of the Related Art

Yield management is important in LCD manufacturing. In LCD manufacturing, a single large plate of glass is divided into just a handful of LCD panels. As consumer demand grows for larger and larger displays, substrates get larger and the number of LCD panels per glass plate decreases. Accordingly, production yields are critical in LCD manufacturing.

The majority of the costs of an LCD panel comes from manufacturing. As a result, profitability is closely linked to yield rates. Any changes in yield rates will have a financial impact.

LCD panel production is a highly automated process involving various manufacturing stages. Each manufacturing stage consists of many complex steps. For example, one stage of the process creates the thin-film transistor arrays on the glass substrate, which includes multiple passes of thin film deposition, resist layers, exposure, development, etching and stripping. The opportunities for defects occur at nearly every step of every stage in the manufacturing process.

Defects take several different forms, and can generally be divided into optical, mechanical and electrical defects. Some of these defects can be repaired, while others are permanent and may be severe enough to render the LCD panel unusable.

Optical defects are the most common defect. When this type of defect is present, a pixel is “stuck” in either a bright state, in which the pixel always transmits light, or a dark state, in which the pixel never transmits light. The most common cause for this type of defect is an electrical problem, such as a short or an open circuit in the cell's transistor or signal leads. Light or dark spots can also be caused by foreign particle contamination between the glass plates, or between the LCD panel and the backlight.

Another type of optical defect is non-uniformity, which can be caused by non-uniform cell gaps that result in varying thickness of the liquid crystal layer. Uniformity problems can also be caused by errors in the rubbing process for liquid crystal alignment layers, inconsistent color filter thickness or incomplete removal of chemical residues.

Mechanical defects can include broken glass and broken electrical connections. Broken electrical connections can arise from improper assembly, errors in alignment of the components and/or mishandling.

Some LCD manufacturers use testing and inspection equipment that can automatically evaluate panels at intermediate points in the manufacturing process. In some cases, the defects can be automatically repaired. However, comprehensive testing in the LCD production process slows down production. In addition, there are capital and maintenance costs associated with the test equipment. Accordingly, manufacturers have to balance the need for comprehensive and accurate testing against the need to avoid slowing production as much as possible.

SUMMARY OF THE INVENTION

An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.

To achieve the objects, and in accordance with the purpose of the invention, as embodied and broadly described herein, the present invention provides a system and method of monitoring LCD production yields, predicting the effects of different testing methodologies on LCD production yields, and optimizing production yields by comparing the effect of different testing methodologies on the yield at various stages in the LCD testing and assembly process. The present invention can also be used to predict the effect of different testing methodologies on user-defined parameters, such as profit.

In a preferred embodiment, the different testing methodologies are evaluated using a common production run. This reduces the number of LCD panels required to test the different methodologies, and also reduces the probability of LCD panels being sacrificed when an improper testing methodology is applied.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary still in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:

FIG. 1A is a block diagram of the process flow for TFT-LCD fabrication, in accordance with the present invention;

FIG. 1B is a block diagram of one preferred embodiment of the processor of FIG. 1A;

FIG. 2 is a block diagram of the assembly stage 200 of the process flow shown in FIG. 1;

FIG. 3 is a plot showing the pixel voltage distribution when half of the pixels of the TFT-array panel have positive pixel voltages and the other half have negative pixel voltages, in accordance with the present invention;

FIG. 4 is a block diagram showing the layout of a typical glass substrate 400 used in TFT-LCD manufacturing;

FIG. 5 is a flow chart of a method of generating the distribution functions for normal pixels and defective pixels in an actual production environment, in accordance with the present invention;

FIG. 6 is a defect sorting table, in accordance with the present invention;

FIG. 7 is a flow chart of a process for sorting defective pixels discovered using the results of the array test stage, array repair stage, cell inspection stage and module inspection stage, in accordance with the present invention;

FIG. 8 is a revised defect sorting table for primary-test-only at the TFT-array test stage, in accordance with the present invention;

FIG. 9 is a revised defect sorting table for new-test-only at the TFT-array test stage, in accordance with the present invention;

FIG. 10 is a flow chart of a process for profit maximization for the TFT-LCD production line can be achieved by optimization of the thresholding parameters, in accordance with the present invention;

FIG. 11 is a flow chart of a process for initial defect sorting, in accordance with the present invention;

FIG. 12 is a flow chart of a process for defect resorting for new screen thresholding, in accordance with the present invention;

FIGS. 13A-13D illustrate a flow chart of a process for profit maximization of new and primary test recipes, in accordance with the present invention;

FIG. 14 is a defect sorting table for tighter new thresholding parameters for a new test recipe, in accordance with the present invention;

FIG. 15 is a defect sorting table for looser new thresholding parameters for a new test recipe, in accordance with the present invention;

FIG. 16 is a revised defect sorting table, in conjunction with the initial defect sorting of FIG. 11, for primary-test-only at the TFT-array test stage, in accordance with the present invention;

FIG. 17 is a plot showing an example of the distribution of normal and defective pixel voltages of a TFT-array panel, in accordance with the present invention;

FIG. 18 is a plot showing the over-killed and under-killed defects as the threshold parameters are scanned, in accordance with the present invention,

FIG. 19 is a plot showing the differential effect of changing threshold parameters for under-killed defects, in accordance with the present invention;

FIG. 20 is a plot showing the differential effect of changing threshold parameters on over-killed defects, in accordance with the present invention;

FIG. 21 is a plot showing the differential effect of changing threshold parameters on cell and module yields, in accordance with the present invention;

FIG. 22 is a plot showing the differential effect of changing threshold parameters on total monetary benefit, in accordance with the present invention;

FIG. 23 is a plot showing the under-killed defects for different defect density values, in accordance with the present invention;

FIG. 24 is a plot showing the differential effect of changing threshold parameters on the total monetary benefit, in accordance with the present invention; and

FIG. 25 is a plot showing how the profit improvement increases with increasing defect density, in accordance with the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

I. Thin-Film Transistor (TFT) Liquid Crystal Display (LCD) Fabrication

FIG. 1A is a block diagram of the process flow for TFT-LCD fabrication. The fabrication process can be divided into two stages, an array panel fabrication stage 100, in which the thin-film transistor (TFT) array panels are fabricated on a substrate, and a test and assembly stage 200, in which the TFT array panels are tested and the displays are assembled.

In the array panel fabrication stage, the glass substrate on which the TFT array panels are fabricated is cleaned at step 102. Steps 104-110 represent well known process steps for forming TFT array panels on a glass substrate. They consist of a thin film deposition step 104, a photoresist patterning step 106, and etching step 108 and a photoresist stripping and cleaning step 110. Steps 104-110 are repeated for each patterned thin film layer that is deposited on the glass substrate.

Multiple TFT array panels are typically fabricated on each glass substrate, which are also referred to as TFT-array base plates. A display unit, such as an LCD display, utilizes one TFT array panel.

Once the TFT array panels are fabricated on the glass substrate, the TFT array panels proceed to the test and assembly stage 200, during which the TFT array panels are tested, the liquid crystal (LC) cells are assembled and separated, and the electrical connections are made to the liquid crystal cells to yield the liquid crystal modules that will ultimately be used in the LCDs. The assembly stage consists of various substages, including an array test stage 202, an array repair stage 204, a cell assembly stage 206, a cell inspection stage 208, a module assembly stage 210 and a module inspection stage 212. The assembly stage 200 may also optionally include a cell repair stage 214 and a module repair stage 216.

In the array test stage 202, each TFT array panel is tested by driving the panel with a test signal, which will be explained in more detail below. TFT array panels that are determined to be bad (e.g., defective) are sent to the array repair stage 204. The panels that are determined to be good are sent to the cell assembly stage 206. In the array repair stage 204, the bad panels that can be repaired are repaired using techniques known in the art, and the repaired panels are then sent to the cell assembly stage 206.

In the cell assembly stage 206, the LC cells are assembled by laminating front and rear glass plates to the TFT array panels and injecting liquid crystal material between the front and rear glass plates using techniques known in the art. In addition, the individual LC cells are separated from each other at this stage by dicing the TFT array base plate (glass substrate).

The assembled and separated LC cells are then sent to the cell inspection stage 208, where they are inspected for defects. LC cells that are determined to be damaged can be sent to an optional cell repair stage 214. The LC cells that are determined to be good LC cells, and the repaired LC cells, if the optional cell repair stage 214 is implemented, are then sent to the module assembly stage 210.

In the module assembly stage 210, the required electrical connections are made to the LC cells to yield the LCD modules that will ultimately be used in LCDs. The LCD modules then proceed to the module inspection stage 212, where they are tested using techniques known in the art. An optional module repair stage 216 can be used to repair LCD modules that are deemed to be defective at the module inspection stage 212.

A processor 220 sends and receives data to/from the test and assembly stage 200. In a preferred embodiment, shown in FIG. 1B, the processor 220 includes a comparison unit 222 and an estimating unit 224. The comparison unit 222 compares the inputs and outputs of the various substages in the test and assembly stage 200 for different manufacturing setups. The estimating unit 224 receives comparison data from the comparison unit 222, and estimates the effect that a change in the manufacturing setup has on a desired parameter, such as profit. The estimating unit 224 utilizes methodologies that will be described below. The estimate data produced by the estimating unit 224 may be used to optimize the manufacturing setup used by the test and assembly stage 200.

The processor 220 of the present invention is preferably implemented on a server may be implemented on a programmed general purpose computer, a special purpose computer, a programmed microprocessor or microcontroller and peripheral integrated circuit elements, an ASIC or other integrated circuit, a hardwired electronic or logic circuit such as a discrete element circuit, a programmable logic device such as a FPGA, PLD, PLA, or PAL, or the like. In general, any device on which a finite state machine capable of implementing the process steps and routines discussed below can be used to implement the processor 220.

II. Profit Model for TFT-LCD Fabrication

A profit model for TFT-LCD fabrication, in accordance with one embodiment of the present invention, will be described with reference to FIG. 2, which is a block diagram of the assembly stage 200 of the process flow shown in FIG. 1.

The variables used to describe the main process stages of FIG. 2 are defined as follows:

-   I_(A)=Number of input panels to array test stage 202; -   I_(AR)=Number of input panels to array repair stage 204; -   I_(C)=Number of input panels to cell inspection stage 208; -   I_(M)=Number of input panels to module inspection stage 212; -   O_(ATG)=Number of passed panels at array test stage 202; -   O_(ATB)=Number of irreparably bad panels at array test stage 202; -   O_(ATR)=Number of reparable panels at array test stage 202, which is     the same as I_(AR); -   O_(ARG)=Number of passed panels at array repair stage 204; -   O_(ARB)=Number of bad panels at array repair stage 204; -   O_(CG)=Number of passed panels at cell inspection stage 208; -   O_(CB)=Number of irreparably bad panels at cell inspection stage     208; -   O_(MG)=Number of passed panels at module inspection stage 212; and -   O_(MB)=Number of irreparably bad panels at module inspection stage     212.

For the optional production flow stages 214 and 216, the additional variables used are defined as follows:

-   O_(CIR)=Number of reparable panels at cell inspection stage 208; -   O_(MIR)=Number of reparable panels at module inspection stage 212; -   O_(CRG)=Number of passed panels at cell repair stage 214; -   O_(MRG)=Number of passed panels at module repair stage 216; -   O_(CRB)=Number of bad panels at cell repair stage 214; and -   O_(MRB)=Number of bad panels at module repair stage 216.

A model that describes the relationship between profits and variations in yields at cell and module inspections will now be described. Certain cost variables will be used as follows:

-   C_(A)=Cost to make a TFT panel; -   C_(T)=Cost to test a TFT panel; -   C_(R)=Cost to repair a TFT panel; -   C_(C)=Cost of cell assembly for a TFT panel; -   C_(CI)=Cost of cell inspection for a TFT panel; -   C_(M)=Cost of module assembly for a TFT panel; and -   C_(MI)=Cost of module inspection for a TFT panel.

In order to have an initial reference for the evaluation of changes in the manufacturing parameters used in the testing, inspection, or assembly stages, a current manufacturing setup is called a “primary manufacturing setup”, and the results obtained with the primary manufacturing setup are referred to as “primary results.”

The cost analysis is done in connection with the assembly stage 200 of the process flow, without the optional cell repair stage 214 and module repair stage 216. This assumes that there is no difference in costs and output quantities between the primary manufacturing setup and a proposed new manufacturing setup. The cost to manufacture a TFT-LCD panel using the primary setup, COST_(PRIME), can be expressed as follows: COST_(PRIME)=Array manufacturing cost+Array test cost+Array repair cost+Cell assembly cost+Cell inspection cost+Module assembly cost+Module inspection cost.  (1)

One can obtain the expressions for the cost values as follows: Array manufacturing cost=I_(A)C_(A)  (2) Array test cost=I_(A)C_(T)  (3) Array repair cost=I_(AR)C_(R)  (4) Cell assembly cost=I_(C)C_(C)  (5)  Cell inspection cost=I_(C)C_(CI)  (6) Module assembly cost=I_(M)C_(M)  (7) Module inspection cost=I_(M)C_(MI)  (8)

The yields at each stage are defined as follows: Yield of array test (Y _(AT))=O _(ATG) /I _(A)  (9) Yield of array repair (Y _(AR))=O _(ARG) /I _(AR)  (10) Yield of cell inspection (Y _(C))=O _(CG) /I _(C)  (11) Yield of module inspection (Y _(M))=O _(MG) /I _(M)  (12)

Since I_(M)=O_(CG) without the optional cell repair and module repair stages 214 and 216, Equation (11) can be written as: I_(M)=Y_(C)I_(C)  (13) From Equations (1), (2)-(8), and (13) one obtains: COST_(PRIME) =I _(A) C _(A) +I _(A) C _(T) +I _(AR) C _(R) +I _(C) C _(C) +I _(C) C _(CI) +Y _(C) I _(C) C _(MI)  (14)

The value of the final TFT-LCD module output, in the case of the primary manufacturing setup without the optional cell repair and module repair stages 214 and 216, can be expressed as follows: PRODUCT_(PRIME)=O_(MG)P_(VALUE),  (15) where P_(VALUE) is the value of a TFT-LCD module fabricated using the primary manufacturing setup. From Equations (12), (13), and (14), one obtains: PRODUCT_(PRIME)=Y_(M)Y_(C) I _(C)P_(VALUE)  (16)

When a new manufacturing setup is used in the array test stage 202, cell inspection stage 206, module inspection stage 212, cell assembly stage 206, and/or module assembly stage 210, one can expect to have new values represented by the following variables:

-   I′_(AR)=New number of input panels to array repair; -   I′_(C)=New number of input panels to cell inspection; -   I′_(M)=New number of input panels to module inspection; -   O′_(ATG)=New number of passed panels at array test; -   O′_(ATB)=New number of irreparably bad panels at array test; -   O′_(ATR)=New number of reparable panels at array test, which is the     same as I′_(AR); -   O′_(ARG)=New number of passed panels at array repair; -   O′_(ARB)=New number of bad panels at array repair; -   O′_(CG)=New number of passed panels at cell inspection, which is     same as I′_(M); -   O′_(CB)=Number of bad panels at cell inspection; -   O′_(MG)=New number of passed panels at module inspection; -   O′_(MB)=New number of bad panels at module inspection; -   Y′_(AT)=New yield of array test; -   Y′_(AR)=New yield of array repair; -   Y′_(C)=New yield of cell inspection; and -   Y′_(M)=New yield of module inspection.

One can then obtain a new set of expressions for the new manufacturing setup, without the optional cell repair and module repair stages 214 and 216, as follows: COST_(NEW) =I _(A) C _(A) +I _(A) C _(T) +I′ _(AR) C _(R) +I′ _(C) C _(C) +I′ _(C) C _(CI) +Y′ _(C) I′ _(C) C _(M) +Y′ _(C) I′ _(C) C _(MI)  (17) PRODUCT_(NEW)=Y′_(M)Y′_(C)I′_(C)P′_(VALUE),  (18) where P′_(VALUE) is the value of the TFT-LCD module fabricated with the new manufacturing setup.

The profit increase (or deficit decrease), P, that results from the new manufacturing setup is obtained as follows: P=COST_(PRIME)−COST_(NEW)+PRODUCT_(NEW)−PRODUCT_(PRIME)  (19)

From Equations (14), (16), (17), (18), and (19) one obtains the following expression for P: P=(I _(AR) −I′ _(AR))C _(R) +(I _(C) −I′ _(C))C _(C)+(I _(C) −I′_(C))C _(CI) +Y _(C) I _(C) C _(M) Y _(C) I_(C) C _(MI) −Y′ _(C) I′ _(C) C _(M) −Y′ _(C) I′_(C) C _(MI) +Y′ _(M) Y′ _(C) I′ _(C) P′ _(value) −Y_(M) Y _(C) I _(C) P _(VALUE)  (20)

During regular production of a TFT-LCD, one can assume that O_(ATB)+O_(ARB)≅O′_(ATB)+O′_(ARB), because a bad panel usually gets carried to the next process stage, as the individual panels have not yet been separated from each other and are all on a common TFT-array base plate. If this assumption is valid, then with I _(C) =I _(A)−(O _(ATB) +O _(ARB)), and  (21) I′ _(C) =I _(A)−(O′ _(ATB) +O′ _(ARB)),  (22) one obtains: I_(C)≅I′_(C)  (23)

Using Equation (23) in Equation (20), one obtains P≅(I _(AR) −I _(AR))C _(R)+(Y _(C) −Y′ _(C))I _(C)(C _(M) +C _(MI))+(Y′ _(M) Y′ _(C) P′ _(VALUE) −Y _(M) Y _(C) P _(VALUE))I _(C)  (24) Since the value of a TFT-LCD module is irrelevant to the manufacturing setup, one obtains: P_(VALUE)=P′_(VALUE)  (25)

Thus, with Equation (25), Equation (24) can be further simplified as: P≅(I _(AR) −I′ _(AR))C _(R)+(Y _(C) −Y′ _(C))I _(C)(C _(M) +C _(MI))+(Y′ _(M) Y′ _(C) −Y _(M) Y _(C))P _(VALUE) I _(C)  (26) Accordingly, Equation (26) can be used to calculate the profit increase or decrease as a result of the yield variation that occurs due to a new manufacturing setup.

One can use the relationships described above to evaluate the profits and the production quantities needed to achieve a break-even point in TFT-LCD manufacturing. This type of cost analysis is done based on the assumption that no TFT array panels are discarded as bad panels during TFT array process. The cost of TFT-LCD panel (COST) can be expressed as follows: COST=Array manufacturing cost+Array test cost+Array repair cost+Cell assembly cost+Cell inspection cost+Module assembly cost+Module inspection cost+Packaging cost+Storage and transportation cost+Other fixed cost.  (27)

One can obtain additional expressions for the cost values as follows: Packaging cost=I_(M)C_(P); and  (28) Storage and transportation cost=I_(M)C_(S),  (29) where C_(P) and C_(S) are the unit packaging and storage/transportation cost, respectively.

From Equations (2)-(8), (13), (27), (28), and (29) one obtains: COST=I _(A) C _(A) +I _(A) C _(T) +I _(AR) C _(R) +I _(C) C _(C) +I _(C) C _(CI) +Y _(C) I _(C)(C _(M) +C _(MI) +C _(P) +C _(S))+C _(F),  (30) where C_(F) is other fixed costs. The value of the final output, without the optional cell and module repair stages 214 and 216, can be expressed as follows: PRODUCT=O_(MG)D_(SALE).  (31) where D_(SALE) is the sales price of a TFT-LCD product unit.

From Equations (12), (13), and (31), one obtains: PRODUCT=Y_(M)Y_(C)I_(C)D_(SALE).  (32) Then, the profit (PT) is obtained by: PT=PRODUCT−COST.  (33)

From Equations (30), (32), and (33), one obtains: PT=Y _(M) Y _(C) I _(C) D _(SALE)−(I _(A) C _(A) +I _(A) C _(T) +I _(AR) C _(R) +I _(C) C _(C) I _(C) C _(CI) +Y _(C) I _(C)(C _(M) +C _(MI) C _(P) +C _(S))+C _(F)),  (34)

Using Equation (21) in Equation (34), one obtains: PT=Y _(M) Y _(C)(I _(A) −O _(ATB) −O _(ARB))D _(SALE) −(I _(A) C _(A) +I _(A) C _(T) +I _(AR) C _(R) +C _(F) +(I _(A) −O _(ATB) −O _(ARB))(C _(C) C _(CI) +Y _(C) C _(M) +Y _(C) C _(MI) +Y _(C) C _(P) +Y _(C) C _(S))).  (35)

If one defines Y_(T) as: Y _(T)≡(O _(ATB) +O _(ARB))/I _(A),  (36) then Equation (35) becomes: PT=Y _(M) Y _(C) I _(A)(1−Y _(T))D _(SALE)−(I _(A)(C _(A) +C _(T))+I _(AR) C _(R) +C _(F) I _(A)(1−Y _(T))(C _(C) +C _(CI) +Y _(C)(C _(M) +C _(MI) +C _(P) +C _(S)))).  (37)

I_(A) for the break-even point where PT is zero (I_(A-EVEN)) becomes: I _(A-EVEN)=(I _(AR) C _(R) +C _(F))/(Y _(M) Y _(C)(1−Y _(T))D _(SALE)−(C _(A) +C _(T)+(1−Y _(T))(C _(C) +C _(CI) +Y _(C)(C _(M) +C _(MI) +C _(P) +C _(S))))).  (38)

In normal production, one can assume: O_(ATB)<<I_(A)  (39) Thus, with Equation (9), one obtains: I _(AR) =O _(ATR) =I _(A) −O _(ATB) −O _(ATG) ≅I _(A) −O _(ATG) =I _(A)(1−Y _(AT)).  (40)

From Equations (37) and (40), one obtains:

 PT≅Y _(M) Y _(C) I _(A)(1−Y _(T))D _(SALE)−(C _(F) +I _(A)(C _(A) +C _(T)+(1−Y _(AT))C _(R)+(1−Y _(T))(C _(C) +C _(CI) +Y _(C)(C _(M) +C _(MI) +C _(P) +C _(S))))).  (41)

I_(A-EVEN) is again obtained for I_(A), making PT=0 in Equation (41), as follows: I _(A-EVEN) ≅C _(F)/(Y _(M) Y _(C)(1−Y _(T))D _(SALE)−(C _(A) +C _(T)+(1−Y _(AT))C _(R)+(1−Y _(T))(C _(C) +C _(CI) +Y _(C)(C _(M) +C _(MI) +C _(P) +C _(S))))).  (42) Accordingly, the profit and the production quantities needed for break-even can be derived from yield numbers, cost numbers and sales price.

The profit model described above is applicable to a production line model that does not utilize the cell and module repair stages 214 and 216. However, it should be appreciated that the profit model described above can be adapted for a production line model that does utilize the optional cell and model repair stages 214 and 216, while still falling within the scope of the present invention. Further, if the optional cell and module repair stages 214 and 216 are used, but the cell and module repair rates are so low as to not make a significant contribution to the yield rates, then the above-described profit model may be applied.

III. Identifying Defects During TFT-Array Panel Testing

Each TFT-array panel is tested in the array test stage 202 using array testing equipment known in the art. When each TFT-array panel is tested by the array testing equipment, the TFT-array panel is driven by electrical signals and the storage capacitor of each pixel goes through electrical charging and discharging operations in order to achieve certain target voltage signals. The sensor of the array test equipment measures the pixel voltage on the storage capacitor of every pixel of the TFT-array panel. If a pixel has a defect, then the pixel voltage of the defected pixel is different from the pixel voltage of the normal pixels. The difference between the defected pixel voltage and the normal pixel voltage is called a “defect signal.”

FIG. 3 is a plot showing the pixel voltage distribution when half of the pixels of the TFT-array panel have positive pixel voltages and the other half have negative pixel voltages. These distributions can be represented by a statistical distribution function because of the large number of pixels in each TFT-array panel, and because of the sensor's statistical behavior. The distribution function for normal positive pixel voltages 310 is well represented by a normal distribution function as follows: Θp=N _(P) exp[−(v−V _(P))²/(2σ_(P) ²)]/√{square root over (2πσ_(P) ²)},  (43) where Θp represents the distribution function for normal positive pixel voltages, N_(P) is the total number of pixels having normal positive pixel voltages, v is a pixel voltage variable, V_(P) is a mean value and σ_(P) is a standard deviation of the normal distribution function for positive pixel voltages.

N_(P) can be obtained by subtracting the number of defective pixels having positive pixel voltages from the total number of pixels having positive pixel voltages, and can be approximated to be the total number of pixels having positive pixel voltages because the number of defective pixels having positive pixel voltages is far lower than the number of normal pixels having positive pixel voltages.

The distribution function for normal negative pixel voltages 320 is similarly well represented by a normal distribution function as follows: Θn=N _(N) exp[−(v−V _(N))²/(2σ_(N) ²)]/√{square root over (2πσ_(N) ²)},  (44) where Θn represents the distribution function for normal negative pixel voltages, N_(N) is a total number of pixels having normal negative pixel voltage, and V_(N) is a mean value and σ_(N) is a standard deviation of normal distribution function for negative pixel voltages.

N_(N) can be obtained by subtracting the number of defective pixels having negative pixel voltages from the total number of pixels having negative pixel voltages, and can be approximated to be the total number of pixels having negative pixel voltages because the number of defective pixels having negative pixel voltages is far lower than the number of normal pixels having negative pixel voltages. The values of V_(P), σ_(P), V_(N), and σ_(N) can be typically obtained from the array testing equipment.

The plot of FIG. 3 also shows the defective pixel voltage distributions 330 (θph), 340 (θpl), 350 (θnh), and 360 (θnl). θph and θpl represent the defective pixel voltage distributions in response to driving signals that produce positive polarity pixel voltages. θnh and θnl represent defective pixel voltage distributions in response to driving signals that produce negative polarity pixel voltages.

The array testing equipment uses thresholding parameters of Vthi+, Vtlo+, Vthi−, and Vtlo− to detect the defective pixels. Pixels driven to have positive pixel voltages are reported as defective when their pixel voltages fall outside of the positive threshold region between Vthi+ and Vtlo+. Pixels driven to have negative pixel voltages are reported as defective when their pixel voltages fall outside of the negative threshold region between Vthi− and Vtlo−.

Under-Killed and Over-Killed Defects

If a normal pixel exhibits a pixel voltage that is outside of the threshold region, then the normal pixel is wrongly classified as a defective pixel. This erroneous classification is called an “over-killed defect.” If a defective pixel exhibits a pixel voltage that is inside of the threshold region, then the defective pixel is wrongly characterized as a normal pixel. This erroneous classification is called an “under-killed defect.”

Under-killed defects lower the yields at the cell inspection stage 208 (Y_(C)) and/or the yields at the module inspection stage 212 (Y_(M)). Over-killed defects lower the productivity of the array repair equipment used in the array repair stage 204. Therefore it is very important to set the right values for the thresholding parameters, in order to maximize profit or minimize the loss of product fabrication.

IV. Effects of Bad Cells/Modules on the Number of Under-killed Defects

FIG. 4 is a block diagram showing the layout of a typical glass substrate 400 used in TFT-LCD manufacturing. The glass substrate 400 generally consists of multiple TFT-array panels 400 a-400 i, and each panel is used for a display unit assembly. If the display is classified as a bad unit when it has just a single defect, then the number of bad displays is determined as described below.

When there is only one defect in the glass substrate 400, the one defect can fall on any one of the n panels. Thus, one defect causes one bad display unit. Accordingly, the total number of bad panels in the case of single defect in the glass substrate 400 (N_(BAD-PANEL1)) is: N_(BAD-PANEL1)=1.  (45)

When there is second defect in the glass substrate 400, the second defect can fall on any one of the n panels. If the second defect falls on the same panel that the first defect falls on, then the second defect does not result in a new bad panel. However, the second defect will cause a new bad panel if it falls on one of the other panels. Thus the probability of causing another bad panel by a second defect (P₂) becomes: P ₂=(n−1)/n.  (46)

Thus, from Equations (45) and (46), the total number of bad panels in the case of two defects in the glass substrate (N_(BAD-PANEL2)) is: N _(BAD-PANEL2) =N _(BAD-PANEL1) +P ₂=1+(n−1)/n.  (47)

When there is third defect in the glass substrate 400, the third defect can fall on any one of the n panels. If the third defect falls on a panel that already has any number of defects, then the third defect does not result in a new bad panel. However, the third defect will cause a new bad panel if it falls on a panel that has no defect. Thus, the probability of causing another bad panel by the third defect (P₃) is: P ₃ =P _(DOUBLE)(n−1)/n+(1−P _(DOUBLE))(n−2)/n,  (48) where P_(DOUBLE) is the probability of having two defects in the same panel, and is given by: P _(DOUBLE) =n(1/n)(1/n)=1/n.  (49) Thus, P₃ becomes: P ₃=(1/n)(n−1)/n+(1−1/n)(n−2)/n=(n−1)² /n ².  (50)

Thus, from Eqs. (47) and (50), the total number of bad panels in the case of three defects present in the glass substrate 400 (N_(BAD-PANEL3)) is: N _(BAD-PANEL3) =N _(BAD-PANEL2) +P ₃=1+(n−1)/n+(n−1)² /n ².  (51)

When there is fourth defect in the glass substrate 400, the fourth defect can fall on any one of the n panels. If the fourth defect falls on a panel that already has any number of defects, then the fourth defect does not result in a new bad panel. However, the fourth defect results in a new bad panel if it falls on a panel that has no defect. Thus, the probability of causing another bad panel by the fourth defect (P₄) is: P ₄ =P _(TRIPLE)(n−1)/n+P _(DOUBLE-SINGLE)(n−2)/n+(1−P _(TRIPLE) −P _(DOUBLE-SINGLE))(n−3)/n,  (52) where P_(TRIPLE) is the probability of having three defects in the same panel, and is given by: P_(TRIPLE) =n(1/n)(1/n)(1/n)=1/n ²,  (53) and P_(DOUBLE-SINGLE) is the probability of having two defects in the same panel and one defect in different pane, and is given by: P _(DOUBLE-SINGLE) =n(1/n)(1/n)(n−1)/n=(n−1)/n ².  (54) Thus, P₄ becomes:  P ₄=(1/n ²)(n−1)/n +((n−1)/n ²)(n−2)/n +(1−1/n ²−(n−1)/n ²)(n−3)/n =(n−1)/n ³+(n−1)(n−2) /n ³+(1−1/n ²−(n−1)/n ²) (n−3)/n=(n−1+(n−1)(n−2)+(n ²−1−(n−1)) (n−3))/n ³=(n−1+(n−1) (n−2)+n(n−1)(n−3))/n ³=(n−1)(1+n−2+n (n−3))/n ³=(n−1)(n ²−2n−1)/i n³.  (55)

Thus, from Equations (51) and (55), the total number of bad panels in the case of four defects present in the glass substrate 400 (N_(BAD-PANEL4)) is: N _(BAD-PANEL4) =N _(BAD-PANEL3) +P ₄=1+(n−1)/n+(n−1)² /n ²+(n−1)(n ²−2n−1)/n ³  (56)

In a normal production line, it is very rare that the number of defects per glass substrate exceeds four. If the under-killed defects of the TFT-array test equipment are the dominant cause of bad panels at cell and module inspections, one can assume that the number of cell and module defects is proportional to the number of under-killed defects as follows: N_(CELL-DEFECT)=αU; and  (57) N_(MODULE-DEFECT)=βU,  (58) where α and β are the proportionality constants for cell and module defects, respectively. Then, from Equations (45), (47), (51), (56), (57), and (58), one can obtain: N_(BAD-CELL1)=α;  (59) N _(BAD-CELL2)=α(1+(n−1)/n);  (60) N _(BAD-CELL3)=α(1+(n−1)/n+(n−1)² /n ²);  (61) N _(BAD-CELL4)=α(1+(n−1)/n+(n−1)² /n ²+(n−1)(n ²−2n−1)/n ³);  (62)  N_(BAD-MODULE1)=β;  (63) N _(BAD-MODULE2)=β(1+(n−1)/n);  (64) N _(BAD-MODULE3)=β(1+(n−1)/n+(n−1)² /n ²); and  (65) N _(BAD-MODULE4)=β(1+(n−1)/n+(n−1)² /n ²+(n−1)(n ²−2n−1)/n ³),  (66) where N_(BAD-CELL) and N_(BAD-MODULE) are the number of bad cells and modules, respectively.

If the number of under-kill defects per glass substrate does not exceed approximately four, and the number of panels per glass substrate (n) is significantly larger than 1, then one obtains: N_(BAD-CELL1)=α;  (67) N_(BAD-CELL2)≅2α;  (68) N_(BAD-CELL3)≅3α;  (69) N_(BAD-CELL4)≅4α;  (70) N_(BAD-MODULE1)=β;  (71) N_(BAD-MODULE2)≅2β;  (72) N_(BAD-MODULE3)≅3β; and  (73) N_(BAD-MODULE4)≅4β.  (74)

Equations (67) to (70) can be summarized as: N_(BAD-CELL)≅Uα,  (75) and Equations (71) to (74) can be summarized as:  N_(BAD-MODULE)≅Uβ.  (76) V. Test Recipes

Ideally, the array testing equipment is supposed to identify all the defective pixels in the TFT-array panel without misclassifying normal pixels as a defective pixels. However, in reality, the array testing equipment may miss actual defective pixels (under-killed defects) and wrongly classify normal pixels as defective pixels (over-killed defects).

The phrase “test recipe” is used herein to refer to the testing parameters used by the array testing equipment, e.g., the amplitude, timing and shape of the pixel driving signal, and the thresholding parameters used to classify pixels as normal or defective. A currently used recipe is referred to herein as a “primary test recipe”, and its result is called a “primary test result”. A proposed new test recipe is referred to herein as a “new test recipe”, and its result is called a “new test result.”

A new test recipe is classified herein as either a “new thresholding test recipe” or a “new distribution function test recipe.” A new thresholding recipe is one that only changes the thresholding parameters, without affecting the voltage distribution functions of the normal and defective pixels. A new distribution function recipe is one that changes the voltage distribution functions of the normal and/or defective pixels.

VI. Effects of Under-Killed Defects on Profits

When a new test recipe is used in the array testing equipment, the numbers of under-killed and over-killed defects may change from those of the primary test recipe. A method for determining the effects that under-killed defects have on the yields and profits in TFT-LCD manufacturing will now be described. The method described below assumes that the optional cell repair and module repair stages 214 and 216 are not implemented.

If under-killed defects are the dominant cause of bad panels at the cell inspection stage 208 (O_(CB) in FIG. 2), then one can assume that the rate of bad panels at the cell inspection stage 208 is proportional to the number of under-killed defects (refer to Equation (75)), and obtain the following expression: O _(CB) /I _(C) :U=O′ _(CB) /I′ _(C) :U′,  (77) where U is the number of under-killed defects for the primary test recipe and U′ is the number of under-killed defects for the new test recipe. Then, one obtains: O′ _(CB) /I′ _(C) =O _(CB) U′/(I _(C) U).  (78) Without the optional cell and module repair stages 214 and 216, O _(CB) =I _(C) −O _(CG).  (79) Thus, with Equation (78), one obtains: (I′ _(C) −O′ _(CG))/I′ _(C)=(I _(C) −O _(CG))U′/(I _(C) U),  (80) which becomes: 1−O′ _(CG) /I′ _(C)=(1−O _(CG) /I _(C))U′/U.  (81)

From Equations (11) and (81), one obtains: Y′ _(C)=1−(1−Y _(C))U′/U.  (82) Then, the improvement of the yield at the cell inspection stage 208 (E_(YC)) can be expressed as: E _(YC) ≡Y′ _(C) −Y _(C)=(1−Y _(C))(1−U′/U).  (83)

If the under-killed defects are the dominant cause of the bad panels at the module inspection stage 212 (O_(MB) in FIG. 2), then one can also assume that the rate of bad panels at the module inspection stage 212 is proportional to the number of under-killed defects (refer to Equation (76)), and obtain following expression: O _(MB) /I _(M) :U=O′ _(MB) /I′ _(M) :U′.  (84)

Then, one obtains: O′ _(MB) /I′ _(M) =O _(MB) U′/(I _(M) U).  (85) Since O_(MB)=I_(M)−O_(MG) without the optional cell and module repair stages 214 and 216, with Equation (85), one obtains: (I′ _(M) −O′ _(MG))/I′ _(M)=(I_(M) −O _(MG))U′/(I _(M) U),  (86) which becomes: 1−O′ _(MG) /I′ _(M)=(1−O _(MG) /I _(M))U′/U.  (87)

From Equations (12) and (87), one obtains: Y′ _(M)=1−(1−Y _(M))U′/U.  (88) Then, the yield improvement at the module inspection stage 212 (E_(YM)) can be expressed as: E _(YM) ≡Y′ _(M) −Y _(M)=(1−Y _(M))(1−U′/U).  (89)

From Equations (82), (88), and (26), one obtains:

 P≅(I _(AR) −I′ _(AR))C _(R)+(Y _(C)−(1−(1−Y _(C))U′/U))I _(C)(C _(M) +C _(MI))+((1−(1−Y _(M))U′/U)(1−(1−Y_(C))U′/U)−Y _(M) Y _(C))P _(VALUE) I _(C)  (90)

The effect of a new test recipe on the over-killed panels, ΔQ, and on the under-killed panels, ΔU, can be expressed as: ΔQ=Q−Q′=γ(Q−Q′)=γΔQ; and  (91) ΔU=U−U′=γ(U−U′)=γΔU,  (92) where Q and Q′ are the numbers of over-killed defects for the primary and new test recipes, respectively, U and U′ are the numbers of under-killed defects for the primary and new test recipes, respectively, and γ is a proportionality constant relating the number of defects to the number of bad panels, as shown by Equations (45), (47), (51), and (56).

Then, one can obtain, with the assumption O_(ATB)≅O′_(ATB), I _(AR) −I′ _(AR)=(R+Q−U−O _(ATB))−(R+Q′−U′−O′ _(ATB))≅(Q−Q′)−(U−U′),  (93) where R is the number of bad panels with real defects.

From Equations (91), (92), and (93), one obtains: I _(AR) −I′ _(AR) ≅ΔQ−ΔU=γ(ΔQ−ΔU).  (94) Using Equation (94) in Equation (90), one obtains: P≅γ(ΔQ−ΔU)C _(R)+(Y_(C)−(1−(1−Y _(C))U′/U))I _(C)(C _(M) +C _(MI))+((1−(1−Y _(M))U′/U)(1−(1−Y _(C))U′/U)−Y _(M) Y _(C))P _(VALUE) I _(C)  (95) VI. Profit Maximization by Threshold Optimization

The effect of a new thresholding test recipe on yields at the cell inspection stage 208 and the module inspection stage 212, and on the productivity of the array repair equipment will now be described. It will also be shown how profit can be maximized by optimizing thresholding parameters.

As discussed above, in order to have a reference for optimization of the thresholding parameters, the current test recipe of the array test equipment is called the primary test recipe, and its test result is called the primary test result. The current thresholding parameters of Vthi+, Vtlo+, Vthi−, and Vtlo− are called primary thresholding parameters. If one wants to evaluate the effect of new thresholding parameters on a production batch that has been already been processed through final module inspection using the primary test recipe, then one can use the evaluation method that will now be described.

If the defective pixel voltage distribution is already known, then the number of under-killed defects for the primary test recipe can be obtained by: U=Unl+Unh+Upl+Uph,  (96) where: Unl = ∫_(Vtlo−)^(Vdc−)θ  nl  𝕕v, Unh = ∫_(Vdb−)^(Vthi−)θ  nh𝕕v, Upl = ∫_(Vtlo+)^(Vdb+)θ  pl  𝕕v, Uph = ∫_(Vdc+)^(Vthi+)θ  p  h𝕕v.

If the normal pixel voltage distribution is already known, then the number of over-killed defects for the primary test recipe can be obtained by: Q=Qnl+Qnh+Qpl+Qph,  (97) where: Qnl = ∫_(−∞)^(Vtlo−)Θ  n  𝕕v, Qnh = ∫_(Vthi−)⁰Θ  n𝕕v, Qpl = ∫₀^(Vtlo+)Θ  p  𝕕v, Qph = ∫_(Vthi+)^(∞)Θ  p𝕕v.

The Vtlo− thresholding value is scanned using variable vtlo−, while keeping the other threshold voltages at the fixed primary values. In this way, the number of under-killed and over-killed defects for the new thresholding recipe can be obtained by: U′=U′nl+Unh+Upl+Uph; and  (98) Q′=Q′nl+Qnh+Qpl+Qph,  (99) where: U^(′)nl = ∫_(vtlo−)^(Vdc−)θ  nl  𝕕v  and  Q^(′)nl = ∫_(−∞)^(vtlo−)Θ  n𝕕v.

From Equations (91), (92), and (96)-(99), one obtains: ΔQ=Q−Q′=Qnl−Q′nl; and  (100) ΔU=U−U′=Unl−U′nl.  (101)

From Equations (82), (83), (88), (89), (96), and (98), one obtains: Y′ _(C)=1−(1−Y _(C))(U′nl+Unh+Upl+Uph)/(Unl+Unh+Upl+Uph);  (102) E _(YC) ≡Y′ _(C) −Y _(C)=(1−Y _(C))(1−(U′nl+Unh+Upl+Uph)/(Unl+Unh+Upl+Uph);  (103) Y′ _(M)=1−(1−Y _(M))(U′nl+Unh+Upl+Uph)/(Unl+Unh+Upl+Uph); and  (104) E _(YM) ≡Y′ _(M) −Y _(M)=(1−Y _(M))(1−(U′nl+Unh+Upl+Uph)/(Unl+Unh+Upl+Uph).  (105)

From Equations (95), (96), (98), (100), and (101), one obtains:

 P≅γ(Qnl−Q′nl−Unl+U′nl)C _(R) +(Y _(C)−(1−(1−Y _(C)) (U′nl+Unh+Upl+Uph)/(Unl+Unh+Upl+Uph)))I _(C) (C _(M) +C _(MI))+((1−(1−Y _(M)) (U′nl+Unh+Upl+Uph)/(Unl+Unh+Upl+Uph))(1 −(1−Y _(C)) U′nl+Unh+Upl+Uph)/(Unl+Unh+Upl+Uph)) −Y _(M) Y _(C))P _(VALUE) I _(C)  (106)

Therefore, profit maximization can be achieved by taking the maximum value of P while the variable vtlo− is scanned around the primary thresholding parameter of Vtlo−.

The Vthi− thresholding value can also be scanned using variable vthi−, while keeping the other thresholding voltages at the fixed primary values. The number of under-killed and over-killed defects for the new thresholding recipe can then be obtained by: U′=Unl+U′nh+Upl+Uph; and  (107) Q′=Qnl+Q′nh+Qpl+Qph,  (108) where: U^(′)nh = ∫_(Vdb−)^(vthi−)θ  nh  𝕕v  and  Q^(′)nh = ∫_(vthi−)⁰Θ  n𝕕v.

From Equations (91), (92), (96), (97), (107), and (108), one obtains: ΔQ=Q−Q′=Qnh−Q′nh; and  (109) ΔU=U−U′=Unh−U′nh.  (110)

From Equations (82), (83), (88), (89), (96), and (107), one obtains: Y′ _(C)=1−(1−Y _(C))(Unl+U′nh+Upl+Uph)/(Unl+Unh+Upl+Uph);  (111) E _(YC) ≡Y′ _(C) −Y _(C)=(1−Y _(C))(1−(Unl+U′nh+Upl+Uph)/(Unl+Unh+Upl+Uph));  (112) Y′ _(M)=1−(1−Y _(M))(Unl+U′nh+Upl+Uph)/(Unl+Unh+Upl+Uph); and  (113)  E _(YM) ≡Y′ _(M) −Y _(M)=(1−Y _(M))(1−(Unl+U′nh+Upl+Uph)/(Unl+Unh+Upl+Uph)).  (114)

From Equations (95), (96), (107), (109), and (110), one obtains: P≅γ(Qnh−Q′nh−Unh+U′nh)C _(R) +(Y _(C)−(1−(1−Y _(C))(Unl+U′nh+Upl+Uph) /(Unl+Unh+Upl+Uph)))I _(C)(C _(M) +C _(MI))+((1 −(1−Y _(M))(Unl+U′nh+Upl+Uph) /(Unl+Unh+Upl+Uph))(1−(1Y _(C)) (Unl+U′nh+Upl+Uph)/(Unl+Unh+Upl+Uph)) −Y _(M) Y _(C))P _(VALUE) I _(C)  (115) Therefore, profit maximization can be achieved by taking the maximum value of P, while the variable vthi− is scanned around the primary parameter of Vthi−.

Thresholding value Vtlo+ can also be scanned using variable vtlo+, while keeping the other thresholding voltages at the fixed primary values. The number of under-killed and over-killed defects for the new thresholding recipe can then be obtained by: U′=Unl+Unh+U′pl+Uph; and  (116) Q′=Qnl+Qnh+Q′pl+Qph,  (117) where: U^(′)pl = ∫_(vtlo+)^(Vdb+)θ  pl  𝕕v  and  Q^(′)pl = ∫₀^(vtlo+)Θ  p𝕕v.

From Equations (91), (92), (96), (97), (116), and (117), one obtains: ΔQ=Q−Q′=Qpl−Q′pl; and  (118) ΔU=U−U′=Upl−U′pl.  (119)

From Equations (82), (83), (88), (89), (96), and (116), one obtains: Y′ _(C)=1−(1−Y _(C))(Unl+Unh+U′pl+Uph)/(Unl+Unh+Upl+Uph);  (120)  E _(YC) ≡Y′ _(C) −Y _(C)=(1−Y _(C))(1−(Unl+Unh+U′pl+Uph)/(Unl+Unh+Upl+Uph));  (121) Y′ _(M)=1−(1−Y _(M))(Unl+Unh+U′pl+Uph)/(Unl+Unh+Upl+Uph); and  (122) E _(YM) ≡Y′ _(M) −Y _(M)=(1−Y _(M))(1−(Unl+Unh+U′pl+Uph)/(Unl+Unh+Upl+Uph)  (123)

From Equations (95), (96), (116), (118), and (119), one obtains: P≅γ(Qpl−Q′pl−Upl+U′pl)C _(R) +(Y _(C)−(1−(1−Y _(C)) (Unl+Unh+U′pl+Uph)/(Unl+Unh+Upl+Uph)))I _(C) ((C _(M) +C _(MI))+((1−(1−Y _(M))(Unl+Unh+U′pl+Uph) /(Unl+Unh+Upl+Uph))(1−(1−Y _(C)) Unl+Unh+U′pl+Uph)/(Unl+Unh+Upl+Uph))−Y _(M) Y _(C))P _(VALUE) I _(C).  (124) Therefore, profit maximization can be achieved by taking the maximum value of P, while the variable vtlo+ is scanned around the primary parameter of Vtlo+.

Thresholding value Vthi+ can also be scanned using variable vthi+, while keeping the other thresholding voltages at the fixed primary values. The number of under-killed and over-killed defects for the new thresholding recipe can then be obtained by: U′=Unl+Unh+Upl+U′ph; and  (125) Q′=Qnl+Qnh+Qpl+Q′ph,  (126) where: U^(′)  p  h = ∫_(Vdc+)^(vthi+)θ  p  h  𝕕v  and  O^(′)p  h = ∫_(vthi+)^(∞)Θ  p𝕕v.

From Equations (91), (92), (96), (97), (125), and (126), one obtains: ΔQ=Q−Q′=Qph−Q′ph; and  (127) ΔU=U−U′=Uph−U′ph.  (128)

From Equations (82), (83), (88), (89), (96), and (125), one obtains:

 Y′ _(C)=1−(1−Y _(C))(Unl+Unh+Upl+U′ph)/(Unl+Unh+Upl+Uph);  (129) E _(YC) ≡Y′ _(C) −Y _(C)=(1−Y _(C))(1−(Unl+Unh+Upl+U′ph)/(Unl+Unh+Upl+Uph));  (130) Y′ _(M)=1−(1−Y _(M))(Unl+Unh+Upl+U′ph)/(Unl+Unh+Upl+Uph); and  (131) E _(YM) ≡Y′ _(M) −Y _(M)=(1−Y _(M))(1−(Unl+Unh+Upl+U′ph)/(Unl+Unh+Upl+Uph)).  (132)

From Equations (95), (96), (125), (127), and (128), one obtains: P≅γ(Qph−Q′ph−Uph+U′ph)C _(R) +(Y _(C)−(1−(1−Y _(C))(Unl+Unh+Upl+U′ph) /(Unl+Unh+Upl+Uph)))I _(C) (C _(M) +C _(MI))+((1−(1−Y _(M)) (Unl+Unh+Upl+U′ph)/(Unl+Unh+Upl+Uph)) (1−(1−Y _(C)) (Unl+Unh+Upl+U′ph) /(Unl+Unh+Upl+Uph))−Y _(M) Y _(C))P _(VALUE) I _(C).  (133) Therefore, profit maximization can be achieved by taking the maximum value of P, while the variable vthi+ is scanned around the primary parameter of Vthi+.

Thus, it has been shown how new values for the thresholding parameters of Vtlo−, Vthi−, Vtlo+, and Vthi+ can be determined that give the maximum profit when the defective and normal pixel voltage distributions are already known. One can use the methodology described above to optimize the thresholding parameters based on presumed or known distributions of defective and normal pixel voltages.

FIG. 5 is a flow chart of a method of generating the distribution functions for normal pixels and defective pixels in an actual production environment. All the equations having integral expressions should be solved in such a way that the integration is performed numerically by counting the number of either good pixels for Θn and Θp, or the number of defective pixels for θnl, θnh, θpl and θph, as the thresholding parameter is scanned.

The method starts at step 500, and proceeds to step 505, where a new thresholding parameter set is used that will classify more pixels as defects than those classified by the primary thresholding parameters. The resulting defect file is labeled “proto defect file”.

Then, at step 510, the proto defect file is reprocessed using the primary thresholding parameters, in order to convert the proto defect file to a primary defect file. The primary defect file is then compared to the proto defect file, and the additional defective pixels reported in the proto defect file are labeled “additional defects”.

Next, at step 515, the defective panels are repaired based on information in the primary defect file. The process proceeds to step 520, where the cells are assembled and inspected.

Then, at step 525, the modules are assembled and inspected. Next, at step 530, if the “additional defects” are detected as real defective pixels during the cell or module inspections, the “additional defects” are used to construct θnl, θnh, θpl, and θph in accordance with the polarity and magnitude of the pixel voltages, as shown in FIG. 3. The process then ends at step 535.

The analysis described above is applicable to a production line model that does not utilize the optional cell and module repair stages 214 and 216. However, it should be appreciated that the analysis described above can be adapted for a production line model that does utilize the optional cell and model repair stages 214 and 216, while still falling within the scope of the present invention. Further, if the optional cell and module repair stages 214 and 216 are used, but the cell and module repair rates are so low as to not make a significant contribution to the yield rates, then the above-described analysis may be applied.

VII. Profit Evaluation Using New Distribution Function Test Recipe

It was described above how profit can be maximized by optimizing the thresholding parameters, based on the assumption that the under-killed defects are the dominant cause of bad panels at the cell and module inspection stages 208 and 212. In order to further improve the profit, a new distribution function test recipe can also be applied to the TFT-array test equipment.

In order to verify the effect of the new distribution function test recipe, one may split a very large production run into two groups, and test one group using the primary test recipe and the second group using the new distribution function test recipe. Then, the yields at the cell and module inspection stages 208 and 212 for each group can be compared. However, this method would take a long time due to the very large sample quantity required to minimize process fluctuations, and also takes the high risk of sacrificing many sample units if one uses an improper new distribution function test recipe.

Thus, it is preferable to evaluate the new distribution function test recipe using the same production run that was already tested with the primary test recipe, in order to obtain a fair comparison between the primary and new distribution function test recipes, without the need for large numbers of panels. The new distribution function test recipe generates different distribution functions for normal and defective pixel voltages from those generated by the primary test recipe, even for the same sample production run. The effects of the new distribution function test recipe on the yield and profit are then evaluated.

First, at the array test stage 202, the sample production run is tested with the primary test recipe, and the test results is labeled “primary defect file” (DF_(PRIME)). Then, the same sample production run is retested with the new distribution function test recipe, and that test result is called “new defect file” (DF_(NEW)).

The sample production run then proceeds to the array repair stage 204, and only the pixels commonly reported as defective in DF_(PRIME) and DF_(NEW) are reviewed by the operator of the TFT-array repair equipment. The operator then attempts to repair the pixels when the defects are visually confirmed. The sample production run then proceeds to next stages, which is assumed to not include the optional cell and module repair stages 214 and 216.

For evaluation of the new distribution function test recipe, one needs to sort out the defects reported in DF_(PRIME) and DF_(NEW) based on the repair actions performed on the defects, and the results of cell and module inspections at the cell and module inspection stages 208 and 212.

The table shown in FIG. 6 and the flow chart shown in FIG. 7 illustrate how the results of the array test stage 202, array repair stage 204, cell inspection stage 208 and module inspection stage 212 are used to sort out the defective pixels discovered.

The process of FIG. 7 starts at step 700, and proceeds to steps 705, where the DF_(PRIME) and DF_(NEW) are obtained from the table of FIG. 6 and sorted as follows:

-   Common defects, CD=(GGc+GGm+OOn+GGcr+GGmr+GGr); -   DF_(PRIME) unique defects, DPu=(GUc+GUm+OGn); and -   DF_(NEW) unique defects, DNu=(UGc+UGm+GOn).

The process then continues to step 710 where, using the input to the array repair stage 204, CD is sorted into:

-   CD1=(GGc+GGm+OOn); and -   CD2=(GGcr+GGmr+GGr).     The array repair stage looks at only CD and parts of them are sorted     as CD2 when a repair action is taken.

Next, at step 715, using the input to the cell inspection stage 208, the following sorting is done:

-   CD1 into GGc and CD1a=(GGm+OOn); -   CD2 into GGcr and CD2a=(GGmr+GGr); -   DPu into GUc and DPu1=(GUm+OGn); -   DNu into UGc and DNu1=(UGm+GOn); and -   new cell defects as UUc.

Then, at step 720, using the input to the module inspection stage, the following sorting is done:

-   CD1a into GGm and OOn; -   CD2a into GGmr and GGr; -   DPu1 into GUm and OGn; -   DNu1 into UGm and GOn; and -   new cell defect as UUm.

The process then ends at step 725. From FIG. 6, the total cell defect for the sample production (T_(CDc)) can be obtained as: T _(CDc) =GGc+GUc+GGcr+UGc+UUc.  (134)

The effect of a new distribution function test recipe on the cell yield will now be considered. Total cell defect, if only the primary test recipe had been applied, is shown in the table of FIG. 8, and is given by: T _(CD) =T _(CDc) −Nc GUc,  (135) because all GUc pixels should have been identified as defects and Nc portion of them could have been repaired to good pixels and would have increased GGr. GGr can be defined as: GGr=GGrc+GGrm,  (136) where GGrc is the number of good repaired pixels, which would have been detected as defects at the cell inspection stage 208 had they not been repaired, and GGrm is the number of good repaired pixels which would have been detected as defects at the module inspection stage 212 had they nor been repaired. One can then assume that the number of successfully repaired pixels (Nc) would have followed the successful repair rate for the commonly detected defects, and obtain an expression for Nc as follows: Nc=GGrc/(GGcr+GGrc).  (137)

One can assume that the successful repair rate of cell defects is the same as that of module defects (GGcr:GGmr=GGrc:GGrm) and obtain: GGrc=GGcr GGrm/GGmr.  (138)

From Equations (136) and (138), one obtains: GGrc=GGcr(GGtr−GGrc)/GGmr;  (139) GGmr GGrc+GGcr GGrc=GGcr GGr; and  (140) GGrc=GGcr GGr/(GGmr+GGcr).  (141)

From Equations (134), (135), (137) and (141), one obtains: Nc=(GGcrGGr/(GGmr+GGcr))/(GGcr+(GGcrGGr/(GGtnr+GGcr)))=GGcrGGr/(GGcr(GGmr+GGcr)+GGcr GGr)=GGr/(GGmr+GGcr+GGr); and  (142) T _(CD) =T _(CDc) −Nc GUc=GGc+(1−Nc)GUc+GGcr+UGc+UUc.  (143)

From Equations (142) and (143), one obtains: T _(CD) =GGc+(GGmr+GGcr)GUc/(GGmr+GGcr+GGr)+GGcr+UGc+UUc.  (144)

Total cell defects, if only the new distribution function test recipe had been applied, is shown in the table of FIG. 9, and is given by: T′ _(CD) =T _(CDc) −Nc UGc,  (145) because all the UGc pixels should have been identified as defects and Nc number of them could have been repaired to good pixels and would have increased GGr.

From Equations (134) and (145), one obtains: T′ _(CD) =T _(CDc) −Nc UGc=GGc+GUc+GGcr+(1−Nc)UGc+UUc.  (146)

From Equations (142) and (146), one obtains: T′ _(CD) =GGc+GUc+GGcr+(GGmr+GGcr)UGc/(GGmr+GGcr+GGr)+UUc.  (147)

From Equations (143) and (146), the effect on total cell defects (ε_(TCD)) due to using the new distribution function test recipe only instead of only the primary test recipe is given by: ε_(TCD) =T _(CD) −T′ _(CD) =Nc UGc−Nc GUc=Nc(UGc−GUc).  (148)

From FIG. 6, the total module defects for the sample production (T_(MDc)) can be obtained as: T _(MDc) =GGm+GUm+GGmr+UGm+UUm.  (149)

The effect of the new distribution function test recipe on the module yield will now be considered. Total module defects, if only the primary test recipe had been applied is shown in FIG. 8, and is given by:

 T_(MD) =T _(MDc) −Nm GUm,  (150)

because all GUm pixels should have been identified as defects, and Nm number of them could have been repaired to good pixels, which would have increased GGr. Then, one can assume that the portion of successfully repaired pixels follows the successful repair rate for the commonly detected defects, and obtain the following expression for Nm: Nm=GGrm/(GGmr+GGrm).  (151)

From Equation (138), one obtains: GGrm=GGmr GGrc/GGcr.  (152)

From Equations (136) and (152), one obtains: GGrm=GGmr(GGr−GGrm)/GGcr;  (153) GGrm GGcr+GGmr GGrm=GGmr GGr; and  (154) GGrm=GGmr GGr/(GGcr+GGmr).  (155)

From Equations (149), (150), (151) and (155), one obtains: Nm=(GGmrGGr/(GGcr+GGmr))/(GGmr+(GGmrGGr/(GGcr+GGmr)))−GGmrGGr/(GGmr(GGcr+GGmr)+GGmr GGr)=GGr/(GGcr+GGmr+GGr); and  (156) T _(MD) =T _(MDc) −NmGUm=GGm+(1−Nm)GUm+GGmr+UGm+UUm.  (157)

From Equations (156) and (157), one obtains: T _(MD) =GGm+(GGcr+GGmr)GUm/(GGcr+GGmr+GGr)+GGmr+UGm+UUm.  (158)

Total module defects, if only the new distribution function test recipe had been applied, is shown in FIG. 9, and is given by:

 T′ _(MD) =T _(MDc) −Nm UGm,  (159)

because all UGm pixels should have been identified as defects, and Nm number of them could have been repaired to good pixels and would have increased GGr.

From Equations (149) and (159), one obtains: T′ _(MD) =T _(MDc) −NmUGm=GGm+GUm+GGmr+(1−Nm)UGm+UUm.  (160)

From Equations (156) and (160), one obtains: T′ _(MD) =GGm+GUm+GGmr+(GGcr+GGmr)UGm/(GGcr+GGmr+GGr)+UUm.  (161)

From Equations (157) and (160), the effect on total module defects (ε_(TMD)) due to using the new distribution function test recipe only instead of only the primary test recipe is given by: ε_(TMD) =T _(MD) −T′ _(MD) =Nm UGm−Nm GUm=Nm(UGm−GUm).  (162)

The effect of the new distribution function test recipe on over-kill will now be considered. From Equation (91) and FIG. 6, one can obtain: Number of over-killed panels of primary-test-only, Q=γQ=γ(OOn+OGn);  (163) Number of over-killed panels of new-test-only, Q′=γQ′=γ(OOn+GOn); and  (164) ΔQ=Q−Q′=γ(OGn−GOn).  (165)

In TFT-LCD manufacturing, because of the possibility of unsuccessful repair work, the under-killed defects may not be the only dominating source for bad panels at cell or module inspections. Thus, from Equations (45), (47), (51) and (56), one can assume that the rate of bad panels at the cell inspection stage 208 is proportional to the number of total cell defects, and obtain following expressions: O _(CB) /I _(C) :T _(CD) =O′ _(CB) /I′ _(C) :T′ _(CD); and  (166) O′ _(CB) /I′ _(C) =O _(CB) T′ _(CD)/(I _(C) T _(CD)).  (167)

From Equations (79) and (167), one obtains: (I′ _(C) −O′ _(CG))/I′ _(C)=(I _(C) −O _(CG))T′ _(CD)/(I_(C) T _(CD)); and  (168) 1−O′ _(CG) /I′ _(C)=(1−O _(CG) /I _(C))T′ _(CD) /T _(CD).  (169)

From Equations (11) and (169), one obtains: Y′ _(C)=1−(1−Y _(C))T′ _(CD) /T _(CD).  (170) Then, the improvement of cell inspection yield (E_(YC)) can be expressed as: E_(YC) ≡Y′ _(C) −Y _(C)=(1−Y _(C))(1−T′ _(CD) /T _(CD)).  (171)

One can also assume that the rate of bad panels at the module inspection stage 212 is proportional to the number of total module defects, and obtain following expression: O _(MB) /I _(M) :T _(MD) =O′ _(MB) /I′ _(M) :T′ _(MD).  (172) Then, one obtains: O′ _(MB) /I′ _(M) =O _(MB) T′ _(MD)/(I _(M) T _(MD)).  (173)

From Equation (173), since O_(MB)=I_(M)−O_(MG) without the optional cell and module repair stages 214 and 216, one obtains: (I′ _(M) −O′ _(MG))/I′ _(M)=(I _(M) −O _(MG))T′ _(MD)/(I _(M) T _(MD)); and  (174)  1−O′ _(MG) /I′ _(M)=(1−O _(MG) /I _(M))T′ _(MD) /T _(MD).  (175)

From Equations (12) and (175), one obtains: Y′ _(M)=1−(1−Y _(M))T′ _(MD) /T _(MD).  (176) Then, the improvement in the module inspection yield (E_(YM)) can be expressed as: E _(YM) ≡Y′ _(M) −Y _(M)=(1−Y _(M))(1−T′ _(MD) /T _(MD)).  (177)

Then, one can obtain an expression for the profit increase by using Equations (170), (171), (176), (177), and (26), as follows: P≅(I _(AR) −I′AR)C _(R)+(Y _(C)−1)(1−T′ _(CD) /T _(CD))I _(C)(C _(M) C _(MI))+((1(1−Y _(M))T′ _(MD) /T _(MD))(1−(1−Y _(C))T′ _(CD) /T _(CD))−Y _(M) Y _(C))P _(VALUE) I _(C).  (178)

Using Equation (94) in Equation (178), one obtains: P≅(ΔQ−ΔU)C _(R)+(Y _(C)−1)(1−T′ _(CD) /T _(CD))I _(C)(C _(M) +C _(MI))+((1−(1Y _(M))T′ _(MD) /T _(MD))(1−(1−Y _(C))T′ _(CD) /T _(CD))−Y_(M)Y_(C))P _(VALUE) I _(C).  (179)

The effect of the new distribution function test recipe on under-kill will now be considered. From Equation (92) and FIG. 6, one can obtain: Number of under-killed panels of primary-test-only, U=γU=γ(UGc+UUc+UGm+UUm); and  (180) Number of under-killed panels of new-test-only, U′=γU′=γ(GUc+GUm+UUc+UUm),  (181) where U and U′ are the numbers of under-killed defects for the primary and new distribution function test recipes, respectively. From Equations (92), (180) and (181), one obtains the following expression for the effect of the new distribution function test recipe on the under-killed panels: ΔU=U−U′=γ(UGc+UGm−GUc−GUm).  (182)

Using Equations (165) and (182) in Equation (179), one obtains: P≅γ(OGn−GOn−UGc−UGm+GUc+GUm)C _(R)+(Y _(C)−1)(1−T′ _(CD) /T _(CD))I _(C)(C _(M) C _(MI))+((1−(1−Y _(M))T′ _(MD) /T _(MD))(1−(1−Y _(C))T′ _(CD) /T _(CD))−Y _(M) Y _(C))P _(VALUE) I _(C)  (183)

The values of Y_(C) and Y_(M) can be obtained from a recent production that was tested with the primary test recipe, under the assumption that the yields between the recent and sample productions are the same. The values of Y_(C) and Y_(M) can also be obtained from the sample production, as will now be explained.

One can obtain expressions for Y_(C) and Y_(M), similar to the expressions for Y′_(C) and Y′_(M) shown in Equations (170) and (176), from the assumption that the rate of bad panels at cell and module inspection stages 208 and 212 is proportional to the number of total cell and module defects: Y _(C)=1−(1−Y _(Cc))T _(CD) /T _(CDc); and  (184) Y _(M)=1−(1−Y _(Mc))T _(MD) /T _(MDc),  (185) where Y_(Cc) and Y_(Mc) are the cell and module yields, respectively, for the sample production in which only the pixels commonly reported as defects in DF_(PRIME) and DF_(NEW) are sent to the TFT-array repair equipment.

From Equations (134), (144), (149), (158), (184) and (185), one obtains:

 Y _(C)=1−(1−Y _(Cc))(GGc+(GGmr+GGcr)GUc/(GGmr+GGcr+GGr)+GGcr+UGc+UUc)/(GGc+GUc+GGcr+UGc+UUc); and  (186) Y _(M)=1−(1−Y _(Mc))(GGm+(GGcr+GGmr)GUm/(GGcr+GGmr+GGr)+GGmr+UGm+UUm)/(GGm+GUm+GGmr+UGm+UUm).  (187)

The values of I_(C), I_(AR), and I_(M) can be obtained from the recent production with the same quantity of I_(A) that was tested with the primary test recipe, under the assumption that the yields are the same between the recent and sample productions. The values of I_(C), I_(AR), and I_(M) can also be obtained from the sample production, as will now be described.

In regular production of TFT-LCDs, one can assume that O_(ATB)+O_(ARB)≅O_(ATBc)+O_(ARBc) (c denotes the sample production), because the bad panels usually go to next process stage as a portion of the larger TFT-array base plate. If the assumption O _(ATB) +O _(ARB) ≅O _(ATBc) +O _(ARBc)  (188) is valid, then with I _(C) =I _(A)−(O _(ATB) +O _(ARB)) and  (189) I _(Cc) =I _(A)−(O _(ATBc) +O _(ARBc)),  (190) one obtains: I_(C)≅I_(Cc)  (191)

From Equations (93), (163), (164), (180), (181) and FIG. 6, one obtains the following expressions for the sample production, in which only the defects detected both by the primary and new distribution function test recipes are sent to the TFT-array repair equipment: I _(AR) −I _(ARc)=(R+Q−U−O _(ATB))−(R+Qc−Uc−O _(ATBc))≅(Q−Qc)−(U−Uc),  (192) where O_(ATB)−O_(ATBc)≅0 is assumed; Over-killed panels of sample production, Qc=Q∩Q′=γOOn; and  (193) Under-killed panels of sample production, Uc=U∪U′=γ(UGc+UUc+UGm+UUm+GUc+GUm).  (194)

From Equations (163), (180), (192), (193) and (194), one obtains: I _(AR) −I _(ARc)≅γ(OOn+OGn−OOn)−γ(UGc+UUc+UGm+UUm−(UGc+UUc+UGm+UUm+GUc+GUm))=γ(OGn+GUc+GUm).  (195)

The value of γ can be obtained with the assumption that O_(ATBc) is very small compared with other parameters. From Equations (192), (193), (194) and FIG. 6, one obtains: I _(ARc) =R+Qc−Uc=γ(GGc+GUc+GGm+GUm+GGcr+GGmr+GGr+UGc+UUc+UGm+UUm+OOn−(UGc+UUc+UGm+UUm+GUc+GUm))=γ(GGc+GGm+GGcr+GGmr+GGr+OOn).  (196) Thus, from Eq. (196), one obtains: γ=I _(ARc)/(GGc+GGm+GGcr+GGmr+GGr+OOn)  (197)

From Equations (195) and (197), one obtains: I _(AR)≅γ(OGn+GUc+GUm)+I _(ARc) =I _(ARc)(OGn+GUc+GUm)/(GGc+GGm+GGcr+GGmr+GGr+OOn)+I _(ARc) =I _(ARc)(OGn+GUc+GUm+GGc+GGm+GGcr+GGmr+GGr+OOn)/(GGc+GGm+GGcr+GGmr+GGr+OOn).  (198)

From FIG. 2, without the optional cell and module repair stages 214 and 216, and Equation (191), one obtains: I _(M) =O _(CG) =I _(C) −O _(CB); and  (199) I _(Mc) =O _(CGc) =I _(Cc) −O _(CBc) ≅I _(C) −O _(CBc).  (200) From Equations (199) and (200), one obtains: I _(M) ≅I _(Mc) +O _(CBc) −O _(CB).  (201)

From Equation (45), (47), (51) and (56), one can assume that the number of bad panels at the cell inspection stage 208 is proportional to the number of total cell defects, and obtain the following expressions: O_(CB)=δT_(CD); and  (202) O_(CBc)=δT_(CDc),  (203) where δ is a proportionality constant.

From Equations (134) and (203), one obtains: δ=O_(CBc) /T _(CDc) =O _(CBc)/(GGc+GUc+GGcr+UGc+UUc).  (204)

From Equations (144), (202) and (204), one obtains: O _(CB)=(GGc+(GGmr+GGcr)GUc/(GGmr+GGcr+GGr)+GGcr+UGc+UUc)O _(CBc)/(GGc+GUc+GGcr+UGc+UUc).  (205) Thus, from Equations (201) and (205), one obtains: I _(M) ≅I _(Mc) +O _(CBc)−(GGc+(GGmr+GGcr)GUc /(GGmr+GGcr+GGr)+GGcr+UGc+UUc)O _(CBc) /(GGc+GUc+GGcr+UGc+UUc)=I _(Mc) +O _(CBc)(1−(GGc+ (GGmr+GGcr)GUc/(GGmr+GGcr+GGr)+GGcr+UGc+UUc) /(GGc+GUc+GGcr+UGc+UUc)).  (206)

Using Equations (134), (144), (147), (149), (158), (161), (184), (185), (186), (187), (191) and (197) in Equation (183), one obtains: P≅(I _(ARc)/(GGc+GGm+GGcr+GGmr+GGr+OOn)) (OGn−GOn−UGc−UGm+GUc+GUm))C _(R) +((Y _(Cc)−1)(GGc+(GGmr+GGcr)GUc /(GGmr+GGcr+GGr)+GGcr+UGc+UUc) /(GGc+GUc+GGcr+UGc+UUc))(1−(GGc+GUc+GGcr+ (GGmr+GGcr)UGc/(GGmr+GGcr+GGr)+UUc)/(GGc+ (GGmr+GGcr)GUc/(GGmr+GGcr+GGr)+GGcr+UGc+UUc)) I _(Cc)(C _(M) +C _(MI))+((1 −(1−Y _(Mc))(GGm+GUm+GGmr+ (GGcr+GGmr)UGm/(GGcr+GGmr+GGr)+UUm) /(GGm+GUm+GGmr+UGm+UUm))(1−(1−Y _(Cc)) (GGc+GUc+GGcr+(GGmr+GGcr)UGc /(GGmr+GGcr+GGr)+UUc)/(GGc+GUc+GGcr+UGc+UUc)) −(1−(1−Y _(Mc))(GGm+(GGcr+GGmr)GUm/ (GGcr+GGmr+GGr)+GGmr+UGm+UUm)/(GGm+GUm+GGmr+UGm+UUm)) (1−(1−Y _(Cc))(GGc+(GGmr+GGcr)GUc/(GGmr+GGcr+GGr) +GGcr+UGc+UUc)/(GGc+GUc+GGcr+UGc+UUc)))P _(VALUE) I _(Cc).  (207)

The analysis described above is applicable to a production line model that does not utilize the optional cell and module repair stages 214 and 216. However, it should be appreciated that the analysis described above can be adapted for a production line model that does utilize the optional cell and model repair stages 214 and 216, while still falling within the scope of the present invention. Further, if the optional cell and module repair stages 214 and 216 are used, but the cell and module repair rates are so low as to not make a significant contribution to the yield rates, then the above-described analysis may be applied.

VIII. Threshold Optimization with No Assumption About Defects

The threshold optimization methodology described above is based on the assumption that the under-killed defects are the only dominant cause of bad panels at cell and module inspections. Threshold optimization can also be done without the assumption that the under-killed defects are the only dominant cause of the bad panels at cell and module inspections.

FIG. 10 is a flow chart showing how profit maximization for the TFT-LCD production line can be achieved by optimization of the thresholding parameters. The process begins at step 1000, and proceeds to step 1005, where the TFT-array panels are tested, at the array test stage 202, by TFT-array test equipment. The testing is done with “proto thresholding” parameters, which are tighter than the primary thresholding parameters of the primary test recipe. The generated proto defects (PD) file identifies more defective pixels than the normal production defects file generated by the primary thresholding. At step 1005, the primary thresholding parameters are set as “screen thresholding parameters” (Pth).

Next, at step 1010, initial defect sorting is performed for the PD file, in accordance with the flow chart of FIG. 11, in which primary thresholding parameters are applied to the proto defects file as screen thresholding parameters (Pth) to screen the PD file and generate a screened defects (SD) file that is identical to the normal defects file generated by the primary thresholding.

Referring to FIG. 11, the initial defect sorting process starts at step 1100, and proceeds to step 1105, where the screened defects (SD) file is generated by using screen thresholding, which screens the PD file by less stringent thresholding parameters than proto thresholding parameters. Then, at step 1110, the SD is reviewed and the panels that are visually confirmed as defective are repaired. The SD that has been repaired is noted as SDrp and is divided into two groups as follows: (1) Successfully repaired pixel (noted as Well)—no defect observed at later inspections; and (2) Still defective due to improper repair. The defect is observed at either cell inspection (noted as CSDrp) or module inspection (noted as MSDrp).

An SD that has not been repaired is noted as SDnr and is divided into two groups as follows: (1) Over-kill at array test (noted as Q)—no defect observed at later inspections; and (2) Defect due to improper visual judge—Defect observed at either cell inspection (noted as CSDnr) or module inspection (noted as MSDnr).

Next, at step 1115, cell inspection confirms the defects reported before and changes the notation as follows:

 PD→CPD SDrp→CSDrp SDnr→CSDnr.

In addition, cell inspection detects new defects (noted as CND): ND→CND.

Then, at step 1120, module inspection confirms the defects reported before and changes the notation as follows: PD→MPD SDrp→MSDrp SDnr→MSDnr. Also, module inspection detects new defects (noted as MND): ND→MND.

If the cell defects are repaired after the cell inspection, then additional sorting is done as follows:

-   (1) Module inspection confirms the defects reported by cell     inspection and changes the notation as follows:     CPD→MCPD CSDrp→MCSDrp CSDnr→MCSDnr CND→MCND; and -   (2) Module inspection confirms the success of repair action done     after cell inspection, and changes the notation as follows:     CPD→RMCPD CSDrp→RMCSDrp CSDnr→RMCSDnr CND→RMCND

The process then ends at step 1125.

Referring back to FIG. 10, the result of the initial defect sorting shown in FIG. 11 is calculated at step 1015 as follows: Cell defect (T _(CD))=CPD+CSDrp+CSDnr+CND;  (208)  Module defect (T _(MD))=MPD+MSDrp+MSDnr+MND; and  (209) Over-kill (Q)=SDnr−(CSDnr+MSDnr).  (210)

After initial defect sorting, the screen thresholding parameters are scanned through the primary thresholding parameters in each zone, so that they can be either tighter or looser than the primary thresholding parameters, but not tighter than the proto thresholding parameters.

Whenever any of the screen thresholding parameters changes its value, defect resorting is done (step 1020) by applying the new parameter to the PD file to determine the effects of the changed parameter. Next, at step 1025, the benefit of the defect resorting is calculated. The process then proceeds to step 1030, where a decision is made as to whether to continue scanning Pth, whose span is set by the user around primary thresholding parameters with a restriction that Pth does not become tighter than the proto thresholding. If it is decided to continue scanning Pth, the process jumps to step 1050. Otherwise, the process continues to step 1035.

At step 1035, the optimum screen thresholding parameters (Pth) is chosen among all the screen thresholding parameters evaluated and its benefit is determined. Next, at step 1040, a decision is made as to whether to try additional screen thresholding parameters based on the benefit determined at step 1035. If it is decided to try additional screen thresholding parameters, the process proceeds to step 1050. Otherwise, the process ends at step 1045.

At step 1050, the screen thresholding parameters are updated, and the process jumps back to step 1020.

FIG. 12 is a flow chart showing the method used for defect resorting (step 1020 of FIG. 10). The process starts at step 1200, and proceeds to step 1205, where it is determined if the screen thresholding is equal to, tighter than, or looser than the primary thresholding. If the screen thresholding is looser than the primary thresholding, then the process jumps to step 1220. If the screen thresholding is equal to the primary thresholding, then the process jumps to step 1230, where the process ends.

If the screen thresholding is tighter than the primary thresholding, then the process proceeds to step 1210, where a new screened defects (SD′) file is generated by using tighter screen thresholding. Tighter screen thresholding decreases the number of PD, increases the number of SD, and decreases the number of CPD and MPD compared to those of primary thresholding. The portion of decrease in the total cell or module defects is given by Rwell, which is defined as the number of well repaired pixel divided by the number of real defects that the repair operator reviews and is expressed as (SDrp−CSDrp−MSDrp)/(SD−Q), based on the assumption that the repair rate is maintained as constant.

At step 1215, the change in CPD (ΔCPD), the change in MPD (ΔMPD) and the change in SD (ΔSD) are calculated. The amount of increase of over-killed defects is given by subtracting the increase of real defect detection, (ΔCPD+ΔMPD), from the increase of screened defects, ΔSD. Thus, when the scanned thresholding parameters are tighter than the primary thresholding parameters, the cell and module defects and over-kill defects ate as follows: T′ _(CD) =CPD+CSDrp+CSDnr+CND−ΔCPD(SDrp−CSDrp−MSDrp)/(SD−Q);  (211) T′ _(MD) =MPD+MSDrp+MSDnr+MND−ΔMPD(SDrp−CSDrp−MSDrp)/(SD−Q); and  (212) Q′=SDnr−(CSDnr+MSDnr)+ΔSD−(ΔCPD+ΔMPD).  (213)

Other parameters can be obtained in a similar way as follows: Cell under-kill, CPD′=CPD−ΔCPD;  (214) CSD′rp=CSDrp+(ΔCPD+ΔMPD)CSDrp/(SD−Q);  (215) CSD′nr=CSDnr+(ΔCPD+ΔMPD)CSDnr/(SD−Q);  (216) Module under-kill, MPD′=MPD−ΔMPD;  (217) MSD′rp=MSDrp+(ΔCPD+ΔMPD)MSDrp/(SD−Q);  (218) MSD′nr=MSDnr+(ΔCPD+ΔMPD)MSDnr/(SD−Q);  (219) MCPD′=MCPD−ΔCPD;  (220) MCSD′rp=MCSDrp+(ΔCPD+ΔMPD)MCSDrp/(SD−Q); and  (221) MCSD′nr=MCSDnr+(ΔCPD+ΔMPD)MCSDnr/(SD−Q).  (222)

From Equations (208) and (211), the change in total cell defects (ε_(TCD)) due to tighter thresholding parameters is given by: ε_(TCD) =T _(CD) −T′ _(CD) =ΔCPD(SDrp−CSDrp−MSDrp)/(SD−Q).  (223)

From Equations (209) and (212), the change in total module defects (ε_(TMD)) due to tighter thresholding parameters is given by: ε_(TMD) =T _(MD) −T′ _(MD) =ΔMPD(SDrp−CSDrp−MSDrp)/(SD−Q).  (224)

From Equations (210) and (213), the change in over-kill defects (ΔQ) due to tighter thresholding parameters is given by: ΔQ=Q−Q′=ΔCPD+ΔMPD−ΔSD.  (225)

From Equations (214) and (217), the change in under-kill defects (ΔU) due to tighter thresholding parameters is given by: ΔU=U−U′=(CPD+MPD)−(CPD′+MPD′)=(CPD+MPD)−(CPD−ΔCPD+MPD−ΔMPD)=ΔCPD+ΔMPD.  (226)

From Equations (170), (171), (176), (177), (208), (209), (211), and (212), one obtains: Y′ _(C)=1−(1−Y _(C))(CPD+CSDrp+CSDnr+CND−ΔCPD(SDrp−CSDrp−MSDrp)/(SD−Q))/(CPD+CSDrp+CSDnr+CND);  (227) E _(YC) ≡Y′ _(C) −Y _(C)=(1−Y _(C))(1−(CPD+CSDrp+CSDnr+CND−ΔCPD(SDrp−CSDrp−MSDrp)/(SD−Q))/(CPD+CSDrp+CSDnr+CND));  (228)  Y′ _(M)=1−(1−Y _(M))(MPD+MSDrp+MSDnr+MND−ΔMPD(SDrp−CSDrp−MSDrp)/(SD−Q))/(MPD+MSDrp+MSDnr+MND); and  (229) E _(YM) ≡Y′ _(M) −Y _(M)=(1−Y _(M))(1−(MPD+MSDrp+MSDnr+MND−ΔMPD(SDrp−CSDrp−MSDrp)/(SD−Q))/(MPD+MSDrp+MSDnr+MND)).  (230)

From Equations (94), (179), (208), (209), (211), (212), (225), and (226), one can obtain the expression for the profit increase from using the tighter thresholding parameters: P≅−γΔSD C _(R)+(Y _(C)−1)(1 −(CPD+CSDrp+CSDnr+CND−ΔCPD (SDrp−CSDrp−MSDrp)/(SD−Q))/(CPD+CSDrp+CSDnr+CND))I _(C) (C _(M) +C _(MI))+((1 −(1−Y _(M))(MPD+MSDrp+MSDnr+MND−ΔMPD (SDrp−CSDrp−MSDrp)/(SD−Q))/(MPD+MSDrp+MSDnr+MND))(1 −(1−Y _(C))(CPD+CSDrp+CSDnr+CND−ΔCPD (SDrp−CSDrp−MSDrp)/(SD−Q))/(CPD+CSDrp+CSDnr+CND)) −Y _(M) Y _(C))P _(VALUE) I _(C).  (231)

The value of γ can be obtained with the assumption that O_(ATB) is very small compared with other parameters, as will now be described. From Equations (91), (92), (93), (210) and (226), one obtains: I _(AR)=γ(R+Q−U)−O_(ATB)≅γ(R+Q−U)=γ((CPD+MPD+SD−Q)+Q−(CPD+MPD))=γSD,  (232) where R is the number of real defects before repair, and is given by: R=CPD+MPD+SD−Q.  (233) Thus, from Equation (232), one obtains:  γ=I _(AR) /SD.  (234)

From Equations (231) and (234), one obtains: P≅−ΔSD C _(R) I _(AR) /SD+(Y _(C)−1)(1 −(CPD+CSDrp+CSDnr+CND−ΔCPD (SDrp−CSDrp−MSDrp)/(SD−Q))/(CPD+CSDrp+CSDnr+CND))I _(C) (C _(M) +C _(MI))+((1−(1−Y _(M)) (MPD+MSDrp+MSDnr+MND−ΔMPD(SDrp−CSDrp−MSDrp) /(SD−Q))/(MPD+MSDrp+MSDnr+MND))(1 −(1−Y _(C))(CPD+CSDrp+CSDnr+CND−ΔCPD (SDrp−CSDrp−MSDrp)/(SD−Q)) /(CPD+CSDrp+CSDnr+CND)) −Y _(M) Y _(C))P _(VALUE) I _(C).  (235) The values of Y_(C), Y_(M), I_(AR), and I_(C) can be obtained from the sample production runs using the primary thresholding parameters.

The use of looser screen thresholding parameters decreases the number of SD and successfully repaired pixels, increases the number of PD, and increases the number of CPD and MPD, compared to using the primary thresholding parameters. In order to analyze the effects of looser screen thresholding parameters, the results of the primary thresholding parameters, given by Equations (208) and (209), are expressed in a different format as follows: T _(CD) =CPD+CSDrp+CSDnr+CND=CPD+CSD′rp+CSD′nr+ΔCSDrp+ΔCSDnr+CND; and  (236) T _(MD) =MPD+MSDrp+MSDnr+MND=MPD+MSD′rp+MSD′nr+ΔMSDrp+ΔMSDnr+MND,  (237) where ΔCSDrp indicates the number of CSDrp that are converted to CPD and is obtained by (CSDrp−CSD′rp), ΔCSDnr indicates the number of CSDnr that are converted to CPD and is obtained by (CSDnr−CSD′nr), ΔMSDrp indicates the number of MSDrp that are converted to MPD and is obtained by (MSDrp−MSD′rp), and ΔMSDnr indicates the number of MSDnr that are converted to MPD and is obtained by (MSDnr−MSD′nr).

The increase in the cell or module defects, which is due to the reduction of the number of successfully repaired pixels, is given by Rwc and Rwm, respectively, based on the assumption that the reverse rate of under-kill defects from the successfully repaired pixels remains constant, and is determined by the following ratios of under-kill defects for the primary thresholding parameters: Rwc=Number of cell under-kill defects/Total number of under-kill defects=CPD/(CPD+MPD); and  (238) Rwm=Number of module under-kill defects/Total number of under-kill defects=MPD/(CPD+MPD).  (239)

Thus, when the scanned thresholding parameters are looser than the primary thresholding parameters, the cell and module defects are given as follows (from Equations (208), (209), (238), and (239)): T′ _(CD) =T _(CD) +ΔWell Rwc=CPD+CSDrp+CSDnr+CND+ΔWell CPD/(CPD+MPD); and  (240) T′ _(MD) =T _(MD) +ΔWell Rwm=MPD+MSDrp+MSDnr+MND+ΔWell MPD/(CPD+MPD),  (241) where ΔWell is the portion of successfully repaired pixels with primary thresholding that would not have been detected with looser thresholding, and become either cell or module under-kill defects. With looser thresholding, the number of over-killed defects is decreased because some portion of Q (ΔQ) would not have been reported as defects. From FIG. 11, one obtains: SD=SDrp+SDnr; and  (242) SDrp=CSDrp+MSDrp+Well,  (243) where Well is the number of successfully repaired defects. From Equations (210), (242) and (243), one obtains the following expression for ΔQ: ΔQ=Q−Q′=(SDnr−(CSDnr+MSDnr))−(SD′nr −(CSD′nr+MSD′nr))=(SD−SDrp −(CSDnr+MSDnr))−(SD′−SD′rp− (CSD′nr+MSD′nr))=(SD− (CSDrp+MSDrp+Well)−(CSDnr+MSDnr))−(SD′− (CSD′rp+MSD′rp+W′ell)−(CSD′nr+MSD′nr))= (SD−SD′)−(CSDrp−CSD′ rp+MSDrp−MSD′rp+Well−W′ell)−(CSDnr−CSD′ nr+MSDnr−MSD′nr)=ΔSD−ΔCSDrp−Δ CSDnr−ΔMSDrp−ΔMSDnr−Δwell.  (244)

Other parameters can be obtained by similar way as follows: Cell under-kill, CPD′=CPD+ΔCSDrp+ΔCSDnr+ΔWell Rwc;  (245) CSD′rp=CSDrp−ΔCSDrp;  (246) CSD′nr=CSDnr−ΔCSDnr;  (247)  Module under-kill, MPD′=MPD+ΔMSDrp+ΔMSDnr+ΔWell Rwm;  (248) MSD′rp=MSDrp−ΔMSDrp;  (249) MSD′nr=MSDnr−ΔMSDnr;  (250) MCPD′=MCPD+ΔCSDrp+ΔCSDnr+ΔWell Rwc;  (251) MCSD′rp=MCSDrp−ΔMCSDrp; and  (252) MCSD′nr=MCSDnr−ΔMCSDnr.  (253)

From Equations (236) and (240), the effect of looser thresholding parameters over the primary thresholding parameters on the total cell defects (ε_(TCD)) is obtained by: ε_(TCD) =T _(CD) =−ΔWell Rwc=−ΔWell CPD/(CPD+MPD).  (254)

From Equations (237) and (241), the effect of looser thresholding parameters over the primary thresholding parameters for the total module defects (ε_(TMD)) is obtained by ε_(TMD) =T _(MD) −T′ _(MD) =−ΔWell Rwm=−ΔWell MPD/(CPD+MPD).  (255)

From Equations (238), (239), (245) and (248), the effect of looser thresholding parameters over the primary thresholding parameters for the under-kill defects (ΔU) is obtained by: ΔU=U−U′=(CPD+MPD)−(CPD′+MPD′) =(CPD+MPD)−(CPD+ΔCSDrp+ΔCSDnr+ΔWell Rwc+MPD+ΔMSDrp+ΔMSDnr+ΔWell Rwm)= −(ΔCSDrp+ΔCSDnr+ΔWell Rwc+ΔMSDrp+ΔMSDnr+ΔWell Rwm)=−(ΔCSDrp+ΔCSDnr+ΔWell+ΔMSDrp+ΔMSDnr).  (256)

From Equations (170), (171), (176), (177), (236), (237), (240) and (241), one obtains: Y′ _(C)=1−(1−Y _(C))(CPD+CSDrp+CSDnr+CND+ΔWell CPD/(CPD+MPD))/(CPD+CSDrp+CSDnr+CND);  (257) E _(YC) ≡Y′ _(C) −Y _(C)=(1−Y _(C))(1−(CPD+CSDrp+CSDnr+CND+ΔWell CPD/(CPD+MPD))/(CPD+CSDrp+CSDnr+CND));  (258) Y′ _(M)=1−(1−Y _(M))(MPD+MSDrp+MSDnr+MND+ΔWell MPD/(CPD+MPD))/(MPD+MSDrp+MSDnr+MND); and  (259) E _(YM) ≡Y′ _(M) −Y _(M)=(1−Y _(M))(1−(MPD+MSDrp+MSDnr+MND+ΔWell MPD/(CPD+MPD))/(MPD+MSDrp+MSDnr+MND)).  (260)

From Equations (244) and (256), one obtains: ΔQ−ΔU=ΔSD.  (261)

From Equations (94), (179), (234), (236), (237), (240), (241) and (261), one can obtain the expression for the profit increase resulting from the looser thresholding parameters as follows: P≅ΔSD C _(R) I _(AR) /SD+(Y _(C)−1)(1 −(CPD+CSDrp+CSDnr+CND+ΔWell CPD /(CPD+MPD))/(CPD+CSDrp+CSDnr+CND))I _(C) (C _(M) +C _(MI))+((1−(1−Y _(M)) (MPD+MSDrp+MSDnr+MND+ΔWell MPD /(CPD+MPD))/(MPD+MSDrp+MSDnr+MND))(1 −(1−Y _(C))(CPD+CSDrp+CSDnr+CND+ΔWell CPD /(CPD+MPD))/(CPD+CSDrp+CSDnr+CND)) −Y_(M) Y _(C))P _(VALUE) I _(C).  (262)

If the cell defects are repaired after the cell inspection stage 208, then the successful rate of cell repair, Rcell, can be obtained from FIG. 11 as follows: Rcell=(RMCPD+RMCSDrp+RMCSDnr+RMCND)/(CPD+CSDrp+CSDnr+CND).  (263)

Once the profit maximization has been achieved for one screen thresholding parameter, then another profit maximization process is performed for another screen thresholding parameter in its scanning zone. This profit maximization process is repeated for all remaining screen thresholding parameters. The data for profit maximization should be obtained from the entire sample production runs, and the optimum screen thresholding parameters are preferably chosen that will maximize the profit for the entire production run.

The analysis described above is applicable to a production line model that does not utilize the optional cell and module repair stages 214 and 216. However, it should be appreciated that the analysis described above can be adapted for a production line model that does utilize the optional cell and model repair stages 214 and 216, while still falling within the scope of the present invention. Further, if the optional cell and module repair stages 214 and 216 are used, but the cell and module repair rates are so low as to not make a significant contribution to the yield rates, then the above-described analysis may be applied.

IX. Profit Maximization of Both Primary and New Test

Profit maximization for both new and primary test recipes using the same sample production runs will now be described. FIGS. 13A-13D illustrate a flow chart for profit maximization of new and primary test recipes.

The process starts at step 1300, and proceeds to step 1302, where sample production runs are tested by the TFT-array test equipment at the array test stage (AT) with a primary distribution function test recipe and primary thresholding parameters (θ_(PRIME)). The test result is labeled primary defect files (DF_(PRIME)). Then, the same sample production runs are retested with the primary distribution function test recipe and 1^(st) proto thresholding, and the test result is labeled “1^(st) PD file.” Then, the same sample production runs are retested with a new distribution function test recipe and 2^(nd) proto thresholding, and the test result is called “2^(nd) PD file.”

Then, at step 1304, thresholding for the new distribution function test recipe (θ_(NEW)), which is looser than the 2^(nd) proto thresholding, is applied to the 2^(nd) PD file to generate defect files labeled DF_(NEW). Next, at step 1306, the sample production runs proceed to the TFT-array repair stage 204 and, as described above in Section VII, only the pixels commonly reported as defects in DF_(PRIME) and DF_(NEW) are reviewed by the operator of the TFT-array repair equipment, and the operator attempts to repair the pixels when the defects are visually confirmed. The sample production runs then proceed to next process stage, which is assumed to have not include the optional cell and module repair stages 214 and 216.

For evaluation of new distribution function test recipe, as described above in Section VII, the defects reported in DF_(PRIME) and DF_(NEW) are sorted out based on the repair actions performed on the defects and the results of cell and module inspections. Then, at step 1308, the effect of the new distribution function test recipe is calculated, as described above in Section VII.

At step 1310, it is decided whether to continue tuning θ_(NEW), whose span is set by the user around the starting θ_(NEW) in step 1304 with a restriction that θ_(NEW) does not become tighter than the 2^(nd) proto thresholding. If the decision is made to not continue θ_(NEW) scanning, then the process jumps to step 1326 (FIG. 13C). Otherwise, the process continues to step 1312.

At step 1312, θ_(NEW) is updated and applied to the 2^(nd) PD file to generate an SD′_(NEW) file. Next, at step 1314, it is determined if θ_(NEW) has been updated to tighter or looser thresholding. If θ_(NEW) is updated to tighter thresholding, then the process proceeds to step 1318, where the values of GUc, GUm, OGn, UUc, UUm and GGn decrease by ΔGUc, ΔGUm, ΔOGn, ΔUUc, ΔUUm, and ΔGGn, respectively, because the SD′_(NEW) files report these as additional defects. FIG. 14 is a table showing how the defect sorting result is modified by the additional defects. In the table of FIG. 14, GGcr is increased by (1−Nc)ΔGUc, GGmr by (1−Nm)ΔGUm, and GGr by NcΔGUc+NmΔGUm, based on the same assumptions used in the table of FIG. 8 above.

If θ_(NEW) is updated to looser thresholding, the process proceeds to step 1316, where the values of GGc, GGm, OOn, GGcr, GGmr, GGr, UGc, UGm, and GOn decrease by ΔGGc, ΔGGm, ΔOOn, ΔGGcr, ΔGGmr, ΔGGr, ΔUGc, ΔUGm, and ΔGOn, respectively, because these are included in the 2^(nd) PD files, but not included in the SD′_(NEW) files as defects. FIG. 15 is a table showing how the defect sorting result is modified by the decrement of reported defects in the SD′_(NEW). In the table of FIG. 15, GUc is increased by ΔGGc+ΔGGcr+ΔGGr GUc/(GUc+GUm) and GUm is increased by ΔGGm+ΔGGmr+ΔGGr GUm/(GUc+GUm), based on the assumption that the reverse rate to GUc or GUm from the successfully repaired pixels when θ_(NEW) becomes looser is maintained constant and is determined by the ratio of GUc and GUm for the starting θ_(NEW).

Once the parameters are updated, as shown in the tables of FIG. 14 or 15, then the effect of the new θ_(NEW) can be obtained by using the analysis of Section VII. Therefore, profit maximization can be achieved by taking the maximum value of P while θ_(NEW) is scanned through the starting θ_(NEW) in its scanning zone. Once the profit maximization has been achieved for one θ_(NEW) parameter, then another profit maximization process is performed for another θ_(NEW) parameter in its scanning zone. This profit maximization process is repeated for all the remaining θ_(NEW) parameters, and is carried out by steps 1312-1324. The data for profit maximization is preferably obtained from the entire sample production runs, and θ_(NEW) parameters are preferably chosen that will maximize profits (P) for the entire production runs.

Once the θ_(NEW) parameters are chosen, the process continues to step 1326, at which a decision is made as to whether to continue scanning primary thresholding parameters (θ_(PRIME)), whose span is set by the user around the starting θ_(PRIME) in step 1302 with a restriction that θ_(PRIME) does not become tighter than the 1^(st) proto thresholding. If a decision is made to continue θ_(PRIME) scanning, then the process continues to step 1328, where θ_(PRIME) is applied to the 1^(st) PD file to generate a defect file labeled SD_(PRIME) file. The parameters shown in FIG. 11 above must be defined for the profit maximization process for the primary test recipe. Since only the pixels commonly reported as defects in DF_(PRIME) and DF_(NEW) were reviewed by the operator of the TFT-array repair equipment, and the operator attempted to repair the pixels when the defects were visually confirmed, the table of FIG. 8 needs to be used for the defect sorting table for the assumed scenario of primary-test-only at the TFT-array test stage 202. By comparing the table of FIG. 8 and FIG. 11, one can obtain the revised defect sorting table in conjunction with the initial defect sorting of FIG. 11, for the assumed scenario of primary-test-only. This table is shown in FIG. 16.

The table of FIG. 16 is used in step 1330, to obtain the parameters of FIG. 11. The expressions for CPD, MPD, CND, and MND are obtained as follows: CPD=(UGc+UUc)∩PD _(PRIME)=(UGc+UUc)∩(1^(st) PD file∩{overscore (SD _(PRIME))});  (264) MPD=(UGm+UUm)∩PD _(PRIME)=(UGm+UUm)∩(1^(st) PD file∩{overscore (SD _(PRIME))});  (265) CND=(UGc+UUc)−CPD; and  (266) MND=(UGm+UUm)−MPD.  (267) Then, Equations (208) to (210) can be used to calculate the effect of the primary-test-only.

At step 1332, for tuning of the primary test recipe, θ_(PRIME) is updated and applied to the 1^(st) PD file to generate the SD′_(PRIME) file. The process then proceeds to step 1334 (FIG. 13D), where it is determined if θ_(PRIME) has been updated to tighter or looser thresholding. If θ_(PRIME) is updated to tighter thresholding, then the process proceeds to step 1338, where the values of CPD and MPD decrease by ΔCPD and ΔMPD, respectively, and the value of SD increases by ΔSD, because the SD′_(PRIME) files report additional defects of ΔSD. The expressions for ΔCPD, ΔMPD, and ΔSD are obtained as follows using Equations (264) and (265): ΔCPD=CPD∩SD′ _(PRIME)=((UGc+UUc)∩PD _(PRIME))∩SD′_(PRIME);  (268) ΔMPD=MPD∩SD′PRIME=((UGm+UUm)∩PD_(PRIME))∩SD′ _(PRIME); and  (269) ΔSD=SD′ _(PRIME) −SD _(PRIME).  (270)

If θ_(PRIME) is updated to looser thresholding, then the process proceeds to step 1336, where the values of CSDrp, CSDnr, MSDrp, MSDnr, Well, and SD decrease by ΔCSDrp, ΔCSDnr, ΔMSDrp, ΔMSDnr, ΔWell, and ΔSD, respectively, because the SD′_(PRIME) files do not report these as defects. The expressions for ΔCSDrp, ΔCSDnr, ΔMSDrp, ΔMSDnr, ΔWell, and ΔSD are obtained as follows using the table of FIG. 16: ΔCSDrp=CSDrp∩PD′ _(PRIME) =GGcr∩PD′ _(PRIME)+(1−Nc)(GUc∩PD′ _(PRIME));  (271) ΔCSDnr=CSDnr∩PD′ _(PRIME) =GGc∩PD′ _(PRIME);  (272) ΔMSDrp=MSDrp∩PD′ _(PRIME) =GGmr∩PD′ _(PRIME)+(1−Nm)(GUm∩PD′ _(PRIME));  (273) ΔMSDnr=MSDnr∩PD′ _(PRIME) =GGm∩PD′ _(PRIME);  (274) ΔWell=Well∩PD′ _(PRIME) =GGr∩PD′ _(PRIME) +Nc(Guc∩PD′ _(PRIME))+Nm(Gum∩PD′PRIME); and  (275) ΔSD=SD _(PRIME) −SD′ _(PRIME),  (276) where PD′_(PRIME)=1^(st PD) file∩{overscore (SD′_(PRIME))}.

Once the parameters are updated using Equations (268) to (270) for tighter θ_(PRIME) and using Equations (271) to (276) for looser θ_(PRIME), then the effect of the new θ_(PRIME) can be obtained by using the analysis of Section VIII. Therefore, profit maximization can be achieved by taking the maximum value of P while θ_(PRIME) is scanned through the starting θ_(PRIME) in its scanning zone. Once the profit maximization has been achieved for one θ_(PRIME) parameter, then another profit maximization process is performed for another θ_(PRIME) parameter in its scanning zone. This profit maximization process is repeated for all the remained θ_(PRIME) parameters, and is carried out by steps 1332-1344. The data for profit maximization should be obtained from the entire sample production runs and θ_(PRIME) parameters are preferably chosen that maximize the profit (P) for the entire production runs. The process then ends at step 1346.

X. Dependence of Thresholding Parameters on Defect Probability

As discussed in Section III, when measuring TFT-array panels using TFT-array test equipment, normal pixels have some voltage distribution around a mean value, as shown in FIG. 3, mainly due to the noise involved in measuring the pixel voltages. This causes some of the normal pixels with extreme noise magnitudes to be falsely reported as defects. The voltage distribution of defective pixels is not always distinct from that of normal pixels, and this causes some of the defective pixels to go through the TFT-array test undetected and become under-killed defects.

In general, tighter thresholding allows less under-killed defects and more over-killed defects, and looser thresholding allows more under-killed defects and less over-killed defects. Some defects exhibit very small defect signals, meaning that their pixel voltages are very close to normal pixel voltages, and very tight thresholding is required to detect these kinds of defects, however, very tight thresholding results in too many over-killed defects. An improved thresholding scheme will now be described that detects more defects, but only increases over-killed defects by a negligibly small amount.

If multiple pixels in very close proximity have some deviation in their pixel voltages from the normal pixel voltage, then tighter thresholding than is needed for an isolated defect should be applied to these pixels, because multiple defects in very close proximity are much more likely to come from a single process abnormality that covers multiple pixels than from multiple isolated defects in close proximity, as will now be explained.

The probability of having the second isolated defect in the area of A_(NEAR) near the first defect (PB_(NT)) is given by “PB_(NT)=A_(NEAR)/A_(TOTAL)”, where A_(TOTAL) is the total display area of the TFT-array panel. The area covering two defects in close proximity (A_(NEAR)) is usually very small compared to A_(TOTAL). If A_(NEAR) is defined by a 10 by 10 pixel array and A_(TOTAL) is 10⁶ pixels, then PB_(NT)=10×10/10⁶=10⁻⁴.

If the probability of a single process abnormality covering two pixels is comparable to that of the first isolated defect, then the probability of having two defects in very close proximity due to a single process abnormality is larger (on the order of about 10⁴ larger) than that due to two isolated defects in close proximity. Therefore, the thresholding should be tighter for multiple defects in close proximity as the number of defects in close proximity increases, because the probability of having multiple defects in very close proximity due to a single process abnormality is increasingly larger on the order of about 10⁴ times the number of multiple defects than that due to multiple isolated defects in close proximity.

Single process abnormalities involving a signal line, such as data, scanning, or common line, can cause multiple defects along the line. The probability of having multiple isolated defects in a linear form is extremely low, based on reasoning similar to that explained above. Thus, the thresholding for defects in a line should also be tighter than the normal thresholding used for an isolated defect.

Process abnormalities can effect a relatively large area of the display, causing many isolated pixels over the relatively large area to have pixel voltages that are slightly deviated from the mean value of normal pixel voltages. Thus, tighter thresholding than that normally used for detecting an isolated defect should be applied to those defects scattered over the relatively large area, if the total number of defects in the defined area exceeds some pre-defined critical number. In general, tighter thresholding should be applied to multiple defects if they are caused by certain single process abnormalities with higher probability.

In some manufacturing lines, additional inspection equipment called automated optical inspection (AOI) equipment may also be used in the TFT array process area to detect process abnormalities in the TFT-array panel. One of the difficulties of this type of inspection is that not every process abnormality detected by the AOI equipment is related to functional defects in the TFT-LCD unit, even though the process abnormalities detected by AOI equipment end up causing functional defects with reasonably high probability. Thus tighter thresholding should be applied to the defects already detected as process abnormalities by the AOI equipment. One can correlate the thresholding of the TFT-array test with the area of process abnormality detected by the AOI equipment, so that tighter thresholding is used as the area of process abnormality gets larger.

Therefore, in order to increase the defect detection efficiency, the first defect file should be generated by the tightest thresholding to detect all the potential defects. Then, the defect file is preferably screened by next tightest thresholding to detect the defects that satisfy the right criteria for that specific thresholding. This procedure is preferably continued until all the different thresholding levels are applied to the potential defects.

XI. Sample Results

As discussed above, the profit of TFT-LCD manufacturing can be maximized by optimizing the parameters of the TFT-array test. The profit maximization is performed by finding the test parameters that strike the right balance between improvement of cell and module yields, and reducing the costs of the TFT-array repair process.

FIG. 17 is a plot showing an example of the distribution of normal 1700 and defective 1710A and 1710B pixel voltages of a TFT-array panel, which are used as the basis of parameter optimization. The distribution of normal pixel voltages 1700 can be represented by a statistical distribution function, because of the large number of pixels per TFT-array panel, and because of sensor's statistical measurement properties. Thus, the distribution of normal pixel voltages 1700 can be well represented by a normal distribution function. The distribution of defect pixel voltages 1710A and 1710B is not fixed, but is dependent on the specific process problems. The distribution of defect pixel voltages 1710A and 1710B is assumed to be constant between arbitrary values of pixel voltages.

As discussed above, TFT-array test equipment uses thresholding parameters to detect the defective pixels. Pixels are reported as defects when their pixel voltages fall outside of the threshold region. If a normal pixel has its pixel voltage outside of the threshold region, then the normal pixel is wrongly reported as a defect and this kind of pixel is called an over-killed defect. If a defective pixel has its pixel voltage within the threshold region, then the defective pixel is wrongly reported as a normal pixel, and this kind of pixel is called an under-killed defect.

FIG. 18 is a plot showing the over-killed and under-killed defects as the thresholding parameters are scanned, based on the distribution of normal and defect pixel voltages shown in FIG. 17.

FIG. 19 is a plot showing the differential effect of changing threshold parameters for under-killed defects, as compared with the results obtained with the primary thresholding parameters, based on the under-killed defects shown in FIG. 18.

FIG. 20 is a plot showing the differential effect of changing threshold parameters on over-killed defects, as compared with the results obtained with the primary thresholding parameters, based on the over-killed defects shown in FIG. 18.

FIG. 21 is a plot showing the differential effect of changing threshold parameters on cell and module yields, as compared with the results obtained with the primary thresholding parameters, based on the differential under-killed defects shown in FIG. 19.

FIG. 22 is a plot showing the differential effect of changing threshold parameters on total monetary benefit, as compared with the results obtained with the primary thresholding parameters, based on the differential effect on over-killed defects shown in FIG. 20 and the differential effect on cell and module yields shown in FIG. 21.

FIG. 23 is a plot showing the under-killed defects for different defect density values. The numbers in the legend indicate the multiplication constants applied to the starting defect density used in FIG. 17.

FIG. 24 is a plot showing the differential effect of changing threshold parameters on the total monetary benefit for the defect densities used in FIG. 23. The numbers in the legend indicate the multiplication constants applied to the starting defect density used in FIG. 17. The profit maximization can be achieved by taking the thresholding parameters that yield the peak points of total monetary benefit, while the thresholding variables are scanned around the primary thresholding parameters.

FIG. 25 is a plot showing how the profit improvement increases with increasing defect density, based on the differential total monetary benefit shown in FIG. 24. The alphabets in the legend indicate the different scanning zones used in FIG. 24.

The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. 

1. A method of estimating a production quantity of electrode array panels required to achieve a predetermined monetary result in a liquid crystal display (LCD) manufacturing setup, wherein the LCD manufacturing setup comprises an array test stage and an array repair stage, comprising: determining, at the array test stage, a number of bad electrode array panels and a number of irreparably bad electrode array panels; determining, at the array repair stage, a number of the bad electrode array panels that are not reparable; determining a first yield parameter based on the number of irreparably bad electrode array panels at the array test stage, and the number of bad electrode array panels that are not reparable at the array repair stage; and estimating the production quantity of electrode array panels for achieving the predetermined monetary result based on the first yield parameter.
 2. The method of claim 1, wherein the predetermined monetary result comprises a break-even point.
 3. The method of claim 1, wherein the LCD manufacturing setup comprises a test recipe used by the array test stage to determine a number of bad electrode array panels to be evaluated by the array repair stage.
 4. The method of claim 3, wherein the test recipe comprises pixel driving signals that are applied to each electrode array panel, wherein pixel voltage distributions are generated in response to the pixel driving signals, and wherein thresholding parameters are applied to the pixel voltage distributions to determine the number of bad electrode array panels.
 5. The method of claim 1, wherein the electrode array panels comprise thin-film transistor (TFT) array panels.
 6. The method of claim 1, wherein the first yield parameter is estimated in accordance with the following relationship: Y _(T)≡(O _(ATB) +O _(ARB))/I _(A), where Y_(T) is the first yield parameter, O_(ATB) is the number of irreparably bad electrode array panels at the array test stage, O_(ARB) is the number of electrode array panels that are not reparable at the array repair stage, and I_(A) is a production quantity of electrode array panels input to the array test stage.
 7. The method of claim 6, wherein the LCD manufacturing setup further comprises a cell assembly stage, a cell inspection stage, a module assembly stage and a module inspection stage, and wherein the method further comprises: determining a cell inspection stage yield; and determining a module inspection stage yield.
 8. The method of claim 7, wherein the production quantity of electrode array panels for achieving the predetermined monetary result is estimated based on the first yield parameter, the cell inspection stage yield and the module inspection stage yield.
 9. The method of claim 8, wherein the production quantity of electrode array panels for achieving the predetermined monetary result is estimated in accordance with the following relationship: PT≅Y _(M) Y _(C) I _(A)(1−Y _(T))D _(SALE)−(C _(F) +I _(A)(C _(A) +C _(T)+(1−Y _(AT))C _(R)+(1Y _(T)) (C _(C) +C _(CI) +Y _(C)(C _(M) +C _(MI) +C _(P) +C _(S))))), where PT is a profit value, Y_(M) is the module inspection stage yield, Y_(C) is the cell inspection yield, I_(A) is a production quantity of electrode array panels input to the array test stage, Y_(T) is the first yield parameter, D_(SALE) is a sales price of a LCD module incorporating an electrode array panel, C_(F) represents fixed costs, C_(A) is a manufacturing cost of an electrode array panel, C_(T) is a cost to test an electrode array panel at the array test stage, C_(R) is a cost to repair an electrode array panel at the array repair stage, C_(C) is a cost to assemble a LCD cell incorporating an electrode array panel, C_(CI) is a cost to inspect a LCD cell incorporating an electrode array panel at the cell inspection stage, C_(M) is a cost to assemble a LCD module incorporating an electrode array panel, C_(MI) is a cost to inspect a LCD module incorporating an electrode array panel, C_(P) is a LCD module packaging cost, and C_(S) is a LCD module storage and transportation cost.
 10. The method of claim 9, wherein a production quantity of electrode array panels for achieving a break-even monetary result is estimated by setting PT to zero.
 11. A system for estimating a production quantity of electrode array panels required to achieve a predetermined monetary result in a liquid crystal display (LCD) manufacturing setup, comprising: an array test stage for testing electrode array panels and determining a number of bad electrode array panels and a number of irreparably bad electrode array panels; an array repair stage for receiving the bad electrode array panels and determining a number of the bad electrode array panels that are not reparable; and a processor for determining a first yield parameter based on the number of irreparably bad electrode array panels at the array test stage and the number of bad electrode array panels that are not reparable at the array repair stage, and for estimating the production quantity of electrode array panels for achieving the predetermined monetary result based on the first yield parameter.
 12. The system of claim 11, wherein the predetermined monetary result comprises a break-even point.
 13. The system of claim 11, wherein the LCD manufacturing setup comprises a test recipe used by the array test stage to determine the number of bad electrode array panels to be received by the array repair stage.
 14. The system of claim 13, wherein the test recipe comprises pixel driving signals that are applied to each electrode array panel, wherein pixel voltage distributions are generated in response to the pixel driving signals, and wherein thresholding parameters are applied to the pixel voltage distributions to determine the number of bad electrode array panels.
 15. The system of claim 11, wherein the electrode array panels comprise thin-film transistor (TFT) array panels.
 16. The system of claim 1, wherein the processor estimates the first yield parameter in accordance with the following relationship: Y _(T)≡(O _(ATB) +O _(ARB))/I _(A), where Y_(T) is the first yield parameter, O_(ATB) is the number of irreparably bad electrode array panels at the array test stage, O_(ARB) is the number of electrode array panels that are not reparable at the array repair stage, and I_(A) is a production quantity of electrode array panels input to the array test stage.
 17. The system of claim 16, further comprising: a cell assembly stage; a cell inspection stage; a module assembly stage; and a module inspection stage.
 18. The system of claim 17, wherein processor estimates the production quantity of electrode array panels for achieving the predetermined monetary based on the first yield parameter, a cell inspection stage yield and a module inspection stage yield.
 19. The system of claim 18, wherein the processor estimates the production quantity of electrode array panels for achieving the predetermined monetary result in accordance with the following relationship: PT≅Y _(M) Y _(C) I _(A)(1−Y _(T))D _(SALE)−(C _(F) +I _(A)(C _(A) +C _(T)+(1−Y _(T)) (C _(C) +C _(CI) +Y _(C)(C _(M) +C _(MI) +C _(P) +C _(S))))), where PT is a profit value, Y_(M) is the module inspection stage yield, Y_(C) is the cell inspection yield, I_(A) is a production quantity of electrode array panels input to the array test stage, Y_(T) is the first yield parameter, D_(SALE) is a sales price of a LCD module incorporating an electrode array panel, C_(F) represents fixed costs, C_(A) is a manufacturing cost of an electrode array panel, C_(T) is a cost to test an electrode array panel at the array test stage, C_(R) is a cost to repair an electrode array panel at the array repair stage, C_(C) is a cost to assemble a LCD cell incorporating an electrode array panel, C_(CI) is a cost to inspect a LCD cell incorporating an electrode array panel at the cell inspection stage, C_(M) is a cost to assemble a LCD module incorporating an electrode array panel, C_(MI) is a cost to inspect a LCD module incorporating an electrode array panel, C_(P) is a LCD module packaging cost, and C_(s) is a LCD module storage and transportation cost.
 20. The system of claim 19, wherein the processor estimates the production quantity of electrode array panels for achieving a break-even monetary result by setting PT to zero.
 21. An article of manufacture, comprising: a computer usable medium having computer readable program code embodied therein for estimating a production quantity of electrode array panels required to achieve a predetermined monetary result in a liquid crystal display (LCD) manufacturing setup, wherein the LCD manufacturing setup comprises an array test stage and an array repair stage, the computer readable program code in the article of manufacture comprising: computer readable program code for causing a computer to determine, at the array test stage, a number of bad electrode array panels and a number of irreparably bad electrode array panels based on a test recipe; computer readable program code for causing a computer to determine, at the array repair stage, a number of the bad electrode array panels that are not reparable; computer readable program code for causing a computer to determine a first yield parameter based on the number of irreparably bad electrode array panels at the array test stage, and the number of bad electrode array panels that are not reparable at the array repair stage; and computer readable program code for causing a computer to estimate the production quantity of electrode array panels for achieving the predetermined monetary result based on the first yield parameter.
 22. The article of manufacture of claim 21, wherein the computer readable program code causes the computer to determine the first yield parameter in accordance with the following relationship: Y _(T)≡(O _(ATB) +O _(ARB))/I _(A), where Y_(T) is the first yield parameter, O_(ATB) is the number of irreparably bad electrode array panels at the array test stage, O_(ARB) is the number of electrode array panels that are not reparable at the array repair stage, and I_(A) is a production quantity of electrode array panels input to the array test stage.
 23. The article of manufacture of claim 21, wherein the LCD manufacturing setup further comprises a cell assembly stage, a cell inspection stage, a module assembly stage and a module inspection stage, and wherein the computer readable program code in the article of manufacture further comprises: computer readable program code for causing a computer to determine a cell inspection stage yield; and computer readable program code for causing a computer to determine a module inspection stage yield.
 24. The article of manufacture of claim 23, wherein the computer readable program code causes the computer to estimate the production quantity of electrode array panels for achieving the predetermined monetary result based on the first yield parameter, the cell inspection stage yield and the module inspection stage yield.
 25. The article of manufacture of claim 24, wherein the computer readable program code causes the computer to estimate the production quantity of electrode array panels for achieving the predetermined monetary result in accordance with the following relationship: PT≅Y _(M) Y _(C) I _(A)(1−Y _(T))D _(SALE)−(C _(F) +I _(A)(C _(A) +C _(T)+(1−Y _(AT))C _(R)+(1−Y _(T)) (C _(C) +C _(CI) +Y _(C)(C _(M) +C _(MI) +C _(P) +C _(S))))), where PT is a profit value, Y_(M) is the module inspection stage yield, Y_(C) is the cell inspection yield, I_(A) is a production quantity of electrode array panels input to the array test stage, Y_(T) is the first yield parameter, D_(SALE) is a sales price of a LCD module incorporating an electrode array panel, C_(F) represents fixed costs, C_(A) is a manufacturing cost of an electrode array panel, C_(T) is a cost to test an electrode array panel at the array test stage, C_(R) is a cost to repair an electrode array panel at the array repair stage, C_(C) is a cost to assemble a LCD cell incorporating an electrode array panel, C_(CI) is a cost to inspect a LCD cell incorporating an electrode array panel at the cell inspection stage, C_(M) is a cost to assemble a LCD module incorporating an electrode array panel, C_(MI) is a cost to inspect a LCD module incorporating an electrode array panel, C_(P) is a LCD module packaging cost, and C_(S) is a LCD module storage and transportation cost.
 26. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for estimating a production quantity of electrode array panels required to achieve a predetermined monetary result in a liquid crystal display (LCD) manufacturing setup, wherein the LCD manufacturing setup comprises an array test stage and an array repair stage, the method steps comprising: determining, at the array test stage, a number of bad electrode array panels and a number of irreparably bad electrode array panels based on a test recipe; determining, at the array repair stage, a number of the bad electrode array panels that are not reparable; determining a first yield parameter based on the number of irreparably bad electrode array panels at the array test stage, and the number of bad electrode array panels that are not reparable at the array repair stage; and estimating the production quantity of electrode array panels for achieving the predetermined monetary result based on the first yield parameter.
 27. The program storage device of claim 26, wherein the first yield parameter is determined in accordance with the following relationship: Y _(T)≡(O _(ATB) +O _(ARB))/I _(A), where Y_(T) is the first yield parameter, O_(ATB) is the number of irreparably bad electrode array panels at the array test stage, O_(ARB) is the number of electrode array panels that are not reparable at the array repair stage, and I_(A) is a production quantity of electrode array panels input to the array test stage.
 28. The program storage device of claim 27, wherein the LCD manufacturing setup further comprises a cell assembly stage, a cell inspection stage, a module assembly stage and a module inspection stage, and wherein the method steps further comprise: determining a cell inspection stage yield; and determining a module inspection stage yield.
 29. The program storage device of claim 28, wherein the production quantity of electrode array panels for achieving the predetermined monetary result is estimated based on the first yield parameter, the cell inspection stage yield and the module inspection stage yield.
 30. The program storage device of claim 29, wherein the production quantity of electrode array panels for achieving the predetermined monetary result is estimated in accordance with the following relationship: PT≅Y _(M) Y _(C) I _(A)(1−Y _(T))D _(SALE)−(C _(F) +I _(A)(C _(A) +C _(T)+(1−Y _(AT))C _(R)(1−Y _(T)) (C _(C) +C _(CI) +Y _(C)(C _(M) +C _(MI) +C _(P) +C _(S))))), where PT is a profit value, Y_(M) is the module inspection stage yield, Y_(C) is the cell inspection yield, I_(A) is a production quantity of electrode array panels input to the array test stage, Y_(T) is the first yield parameter, D_(SALE) is a sales price of a LCD module incorporating an electrode array panel, C_(F) represents fixed costs, C_(A) is a manufacturing cost of an electrode array panel, C_(T) is a cost to test an electrode array panel at the array test stage, C_(R) is a cost to repair an electrode array panel at the array repair stage, C_(C) is a cost to assemble a LCD cell incorporating an electrode array panel, C_(CI) is a cost to inspect a LCD cell incorporating an electrode array panel at the cell inspection stage, C_(M) is a cost to assemble a LCD module incorporating an electrode array panel, C_(MI) is a cost to inspect a LCD module incorporating an electrode array panel, C_(P) is a LCD module packaging cost, and C_(S) is a LCD module storage and transportation cost. 